Efficient and flexible numerical controlled oscillators for navigational receivers
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04B-001/00
H04L-027/06
출원번호
UP-0694296
(2007-03-30)
등록번호
US-7830951
(2010-11-25)
발명자
/ 주소
Jia, Zhike
출원인 / 주소
SiRF Technology Holdings, Inc.
대리인 / 주소
Pillsbury Winthrop Shaw Pittman LLP
인용정보
피인용 횟수 :
1인용 특허 :
14
초록▼
Provided herein are systems and methods for achieving long integration of an input signal by compensating the frequency and phase of each sample of the input signal. In an embodiment, a Numerical Controlled Oscillator (NCO) of the receiver is modified to include a variable control input that allows
Provided herein are systems and methods for achieving long integration of an input signal by compensating the frequency and phase of each sample of the input signal. In an embodiment, a Numerical Controlled Oscillator (NCO) of the receiver is modified to include a variable control input that allows the output frequency of the NCO to be adjusted based on a rate of change of frequency. The rate of change of frequency may be estimated based on the relative velocity of a satellite to the receiver computed from satellite orbit parameters or ephemeris. The rate of change of frequency may also be estimated based on frequency measurements of previous samples. The modified NCO may be used as a carrier NCO or code NCO of the receiver to provide frequency and phase compensation of each sample of the input signal.
대표청구항▼
I claim: 1. A Numerical Controlled Oscillator (NCO) in a navigational receiver, comprising: a frequency step adjuster, wherein the frequency step adjuster is configured to receive a frequency step and a rate of change of frequency, and to adjust the frequency step based on the rate of change of fre
I claim: 1. A Numerical Controlled Oscillator (NCO) in a navigational receiver, comprising: a frequency step adjuster, wherein the frequency step adjuster is configured to receive a frequency step and a rate of change of frequency, and to adjust the frequency step based on the rate of change of frequency; and a counter coupled to the frequency step adjuster, wherein the counter is configured to receive the adjusted frequency step from the frequency step adjuster and an input clock frequency, and to output an output frequency based on the adjusted frequency step and the input clock frequency. 2. The NCO of claim 1, wherein the frequency step adjustor comprises an adder and a register to store the prior frequency. 3. The NCO of claim 1, wherein the frequency step adjustor comprises a register to store the rate of change of frequency in a suitable format. 4. The NCO of claim 1, wherein the rate of change of frequency is in a binary format, and at every 2k input clock pulses, the frequency step adjuster increases or decreases the frequency step by one based on the value of a kth bit of a fractional part of the rate of change of frequency. 5. The NCO of claim 1, further comprising a clock divider to divide the input clock frequency to the frequency step adjuster by a predetermined amount. 6. The NCO of claim 1, wherein the frequency step and the rate of change of frequency to the NCO are set by baseband receiver firmware. 7. The NCO of claim 3, wherein an on-chip or off-chip processor provides the frequency step and the rate of change of frequency to the frequency step adjuster. 8. The NCO of claim 7, wherein the processor is a general purpose DSP, RISC or an ASIC. 9. The NCO of claim 1, wherein the frequency step and the rate of change of frequency inputted to the NCO are adjusted while the NCO is running. 10. The NCO of claim 1, wherein the frequency step and the rate of change of frequency are set based on desired values of the output frequency. 11. The NCO of claim 1, wherein the rate of change of frequency can be set to zero to make the NCO backward compatible with traditional or prior art NCO. 12. The NCO of claim 1, wherein the NCO is implemented at least partially in software or hardware. 13. The NCO of claim 1, wherein the output frequency of the NCO is coupled to a frequency mixer of the receiver. 14. The NCO of claim 1, wherein the output frequency of the NCO is coupled to a pseudorandom (PN) code generator of the receiver. 15. A method of operating a navigation receiver, comprising: receiving a rate of change of frequency and a frequency step at a Numerical Controlled Oscillator (NCO); adjusting the received frequency step based on the received rate of change of frequency to generate an adjusted frequency step; receiving an input clock frequency at the NCO; computing an output frequency as a function of the adjusted frequency step and the input clock frequency; and inputting the output frequency of the NCO to a frequency mixer to wipe off residue carrier frequency or to a pseudorandom (PN) code generator to provide a code frequency. 16. The method of claim 15, further comprising: providing the rate of change of frequency is in a binary format; and at every 2k input clock pulses, increasing or decreasing the frequency step by one based on the value of a kth bit of a fractional part of the rate of change of frequency. 17. The method of claim 15, further comprising: computing Doppler frequencies over time based on relative velocities of a satellite to the receiver; and computing the rate of change of frequency based on the computed Doppler frequencies. 18. The method of claim 17, further comprising: computing the relative velocities of the satellite to the receiver using a satellite orbital model or ephemeris stored in the receiver. 19. The method of claim 17, further comprising: computing the rate of change of frequency by fitting a linear function to the Doppler frequencies. 20. The method of claim 15, further comprising: measuring Doppler frequencies of an input signal over time; and computing the rate of change of frequency based on the measured Doppler frequencies. 21. The method of claim 20, further comprising: computing the rate of change of frequency by fitting a linear function to the Doppler frequencies. 22. The method of claim 15, wherein the NCO comprises a counter, the method further comprising: inputting the adjusted frequency step and the input clock frequency to the counter; increasing a count value of the counter by the adjusted frequency step at each pulse of the input clock frequency; and outputting a pulse from the counter when the count value overflows the counter. 23. The method of claim 22, further comprising: dividing the input clock frequency by a predetermined amount; and inputting the divided clock to adjust the frequency step.
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이 특허에 인용된 특허 (14)
Lennen Gary R. (San Jose CA), Digital bandwidth compression for optimum tracking in satellite positioning system receiver.
Schmidl, Timothy M.; Sriram, Sundararajan, Joint position and carrier frequency estimation method of initial frequency acquisition for a WCDMA mobile terminal.
Wang,Chi Shin; Jia,Zhike; Chen,Yue Meng; Cheng,Jian; Tu,EnYuan, Methods and systems for acquisition, reacquisiton and tracking of weak navigational signals.
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