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Aluminum cap for reducing scratch and wire-bond bridging of bond pads 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 UP-0948073 (2004-09-23)
등록번호 US-7833896 (2011-01-16)
발명자 / 주소
  • Wang, Chung Yu
  • Lee, Chien-Hsiun
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Slater & Matsil, L.L.P.
인용정보 피인용 횟수 : 0  인용 특허 : 44

초록

A method of manufacturing a semiconductor device and structure thereof. The method includes providing a workpiece, the workpiece having at least one conductive pad partially exposed through an opening in a passivation layer, the passivation layer having a top surface and the opening in the passivati

대표청구항

What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: providing a workpiece, the workpiece having at least one conductive pad with an overlying passivation layer; forming an opening in the passivation layer, thereby at least partially exposing the at least

이 특허에 인용된 특허 (44)

  1. Cheung Robin W. ; Lin Ming-Ren, Advanced copper interconnect system that is compatible with existing IC wire bonding technology.
  2. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  3. Chen, Kuo-Chou; Hsu, Huai-Jen, Aluminum-copper bond pad design and method of fabrication.
  4. Shih Wei-Yan ; Wilson Arthur ; Subido Willmar, Bonding pads for integrated circuits having copper interconnect metallization.
  5. Saitoh Kazuto,JPX ; Shoji Reijiro,JPX, Bump structure, bump forming method and package connecting body.
  6. Scholz Kenneth D. (4150 Willmar Dr. Palo Alto CA 94306), Compressive bump-and-socket interconnection scheme for integrated circuits.
  7. Allen McTeer, Copper interconnect for an integrated circuit and methods for its fabrication.
  8. Akram,Salman, Copper interconnect for semiconductor device.
  9. Howell, Wayne J.; Mendelson, Ronald L.; Motsiff, William T., Copper pad structure.
  10. Sudijono, John; Hsia, Liang Ch O; Ping, Liu Wu, Copper recess formation using chemical process for fabricating barrier cap for lines and vias.
  11. Hua,Fay, Electromigration barrier layers for solder joints.
  12. Hsieh,Han Kun; Wang,Shing Ru; Tung,I Chung, Formation of electroplate solder on an organic circuit board for flip chip joints and board to board solder joints.
  13. J. Neal Cox, Method for making integrated circuits.
  14. Lee,Ellis; Huang,Yimin; Yew,Tri Rung, Method making bonding pad.
  15. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding.
  16. Ho, Kwok Keung Paul; Chooi, Simon; Xu, Yi; Aliyu, Yakub; Zhou, Mei Sheng; Sudijono, John Leonard; Gupta, Subhash; Roy, Sudipto Ranendra, Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding.
  17. Kwok Keung Paul Ho SG; Yi Xu SG; Simon Chooi SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding.
  18. Iannuzzi Giulio (Milan ITX) deMartiis Carlo C. (Milan ITX) Del Bo Vittorio (Monza ITX) Gandolfi Luciano (Corsico ITX), Method of connecting semiconductor structure to external circuits.
  19. Lee Ellis,TWX, Method of fabricating copper interconnection.
  20. Hashimoto, Tatsuya; Maenosono, Toshiyuki; Togawa, Taiji; Enda, Takayuki; Takagi, Hideo, Method of fabricating semiconductor memory device and semiconductor memory device driver.
  21. Agarwal, Vishnu Kumar, Method of forming an encapsulated conductive pillar.
  22. Stuart E. Greer, Method of forming copper interconnection utilizing aluminum capping film.
  23. Chen Sheng-Hsiung,TWX, Method of improving copper pad adhesion.
  24. Syun-Ming Jang TW; Mong-Song Liang TW; Chen-Hua Yu TW; Chung-Shi Liu TW; Jane-Bai Lai TW, Method of improving the bondability between Au wires and Cu bonding pads.
  25. Harada Akihiko,JPX ; Saito Takayuki,JPX, Method of manufacturing a semiconductor device.
  26. Gupta Subhash,SGX ; Ho Paul Kwok Keung,SGX ; Zhou Mei Sheng,SGX ; Chockalingam Ramasamy,SGX, Method to avoid copper contamination during copper etching and CMP.
  27. Gupta Subhash,SGX ; Ho Kwok Keung Paul,SGX ; Zhou Mei-Sheng,SGX ; Chool Simon,SGX, Method to avoid copper contamination on the sidewall of a via or a dual damascene structure.
  28. Doan Trung T. (Boise ID) Tuttle Mark E. (Boise ID), Method to form a low resistant bond pad interconnect.
  29. McTeer, Allen, Multi-layered copper bond pad for an integrated circuit.
  30. Misawa Nobuhiro (Kawasaki JPX), Process for fabricating integrated circuit devices.
  31. Daniel C. Edelstein ; Judith M. Rubino ; Carlos J. Sambucetti ; Anthony K. Stamper, Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond.
  32. Catabay, Wilbur G.; Schinella, Richard; Wang, Zhihai; Hsia, Wei-Jen, Process for planarizing upper surface of damascene wiring structure for integrated circuit structures.
  33. Hsu Fang-Jen,TWX ; Fan Chen-Peng,TWX ; Yen Ming-Shuo,TWX ; Chen Chi-Ping,TWX, Process for preventing corrosion of aluminum bonding pads after passivation/ARC layer etching.
  34. Anthony K. Stamper ; Sally J. Yankee, Recessed bond pad.
  35. Anthony K. Stamper ; Sally J. Yankee, Recessed bond pad.
  36. Stamper, Anthony K.; Yankee, Sally J., Recessed bond pad.
  37. Lansford Jeremy, Reduced variation in interconnect resistance using run-to-run control of chemical-mechanical polishing during semiconductor fabrication.
  38. Kobayashi, Kaname, Semiconductor device and method for manufacturing the same.
  39. Tanaka,Masayuki; Saida,Shigehiko; Tsunashima,Yoshitaka, Semiconductor device and method of manufacturing the same.
  40. Downey, Susan H.; Miller, James W.; Hall, Geoffrey B., Semiconductor device having a wire bond pad and method therefor.
  41. Morozumi, Yukio, Semiconductor devices and methods for manufacturing the same.
  42. Hayashi Yoshihiro (Tokyo JPX), Semiconductor structure and method for fabricating the same.
  43. Test, Howard R.; Amador, Gonzalo; Subido, Willmar E., Wire bonding process for copper-metallized integrated circuits.
  44. Sailesh Chittipeddi ; Sailesh Mansinh Merchant, Wire bonding to copper.
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