초록 ▼

A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging b

A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages. A first stage pre-charges all bit lines via PMOS pull-up, and the second stage uses the latches to discharge or leave charged the selected bit lines depending on respective data bits being stored. The gate voltages of NMOS transistors in the programming circuitry can be controlled to reduce noise caused by discharging selected bit lines through the latches.

대표청구항 ▼

I claim: 1. A programming method for a non-volatile memory, comprising: pre-charging a plurality of bit lines to a first voltage, wherein the pre-charging includes connecting a first transistor that is between a supply voltage and the plurality of bit lines into a current mirror circuit that limits

I claim: 1. A programming method for a non-volatile memory, comprising: pre-charging a plurality of bit lines to a first voltage, wherein the pre-charging includes connecting a first transistor that is between a supply voltage and the plurality of bit lines into a current mirror circuit that limits peak current flowing through the first transistor to the plurality of bit lines; discharging a first plurality of bit lines among the plurality of pre-charged bit lines, the first plurality of bit lines corresponding to cell transistors being programmed to store a bit value “0” by connecting a latch circuit; and applying a second voltage to a selected word line to program one or more selected memory cells coupled to the selected word line, wherein the first voltage remains on at least one bit line of the plurality of bit lines and prevents programming of a memory cell coupled to the at least one bit line and the selected word line. 2. The method of claim 1, further comprising: controlling the first transistor to conduct less than a saturation current of the first transistor. 3. The method of claim 1, wherein the pre-charging charges all bit lines that are connected to memory cells that are connected to the selected word line. 4. The method of claim 1, further comprising, maintaining a charge of a second plurality of bit lines among the plurality of bit lines, the second plurality of bit lines corresponding to cell transistors storing a bit value “1.” 5. The method of claim 1, wherein discharging comprises operating a second transistor that conducts a current from the first plurality of bit lines to the latch circuit so that the second transistor conducts less than a saturation current of the second transistor. 6. The method of claim 1, wherein the first voltage is less than the supply voltage.