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Method and apparatus for supporting address translation in a virtual machine environment

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-021/00
  • G06F-009/26
  • G06F-009/34
출원번호 UP-0154627 (2008-05-22)
등록번호 US-7836275 (2011-01-16)
발명자 / 주소
  • Anderson, Andrew V.
  • Kägi, Alain
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 14  인용 특허 : 191

초록

In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based o

대표청구항

What is claimed is: 1. A method comprising: creating a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and deriving metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hiera

이 특허에 인용된 특허 (191)

  1. Ryba Edward G. (Milpitas CA) Lipman Peter H. (Cupertino CA) Connell Jefferson J. (Cupertino CA) Weiss David (Palo Alto CA), Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB).
  2. Hatada Minoru (Ebina JPX) Ishida Hideaki (Kawasaki JPX) Matsushita Masatoshi (Kawasaki JPX), Access control method for multiprocessor systems.
  3. Kaneda Saburo (Yokohama JPX) Tsuchimoto Takamitsu (Kawasaki JPX) Shimizu Kazuyuki (Machida JPX) Ikegami Fujio (Yokohama JPX), Address control system for software simulation.
  4. Ikegaya Hiroshi (Yokohama JPX) Umeno Hidenori (Kanagawa JPX) Kubo Takashige (Hachioji JPX) Ukai Yoshio (Yokohama JPX) Sugama Nobuyoshi (Chigasaki JPX), Address translator.
  5. Osisek Damian L. (Vestal NY), Allocation of address spaces within virtual machine compute system.
  6. Gannon Patrick M. (Poughkeepsie NY) Gum Peter H. (Poughkeepsie NY) Hough Roger E. (Highland NY) Murray Robert E. (Woodstock NY), Apparatus and method for TLB purge reduction in a multi-level machine system.
  7. Davis Derek L., Apparatus and method for a vetted field upgrade.
  8. Victor Webber, Apparatus and method for decreasing the response times of interrupt service routines.
  9. Pearce John J. (DelValle TX), Apparatus and method for limiting access to mass storage devices in a computer system.
  10. Bogin Zohar ; VonBokern Vincent E., Apparatus and method for preventing access to SMRAM space through AGP addressing.
  11. Bealkowski Richard (Delray Beach FL) Blackledge ; Jr. John W. (Boca Raton FL) Cronk Doyle S. (Boca Raton FL) Dayan Richard A. (Boca Raton FL) Dixon Jerry D. (Boca Raton FL) Kinnear Scott G. (Boca Rat, Apparatus and method for preventing unauthorized access to BIOS in a personal computer system.
  12. Brelsford David P. (Hyde Park NY) Cutler Melvin M. (Los Angeles CA) Lafitte Jean-Louis (Moens NY FRX) Gdaniec Joseph M. (Hyde Park NY) Osisek Damian L. (Vestal NY) Plambeck Kenneth E. (Poughkeepsie N, Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virt.
  13. Davis Derek L., Apparatus and method for providing secured communications.
  14. Arnold Todd Weston, Apparatus and method for secure distribution of data.
  15. Schleupen Richard (Ingersheim DEX), Apparatus for safeguarding data entered into a microprocessor.
  16. Heller Andrew R. (Morgan Hill CA) Worley ; Jr. William S. (Endicott NY), Authorization mechanism for transfer of program control or data between different address spaces having different storag.
  17. Chaum David L. (14652 Sutton St. Sherman Oaks CA 91403), Blind unanticipated signature systems.
  18. Green Daniel W., Cache with finely granular locked-down regions.
  19. Pfefferle William Charles, Catalytic method.
  20. Salt Tom (Chandler AZ) Drake Rodney (Mesa AZ), Code protection in microcontroller with EEPROM fuses.
  21. Ermolovich Thomas R. (Lexington MA) Stewart Robert E. (Stow MA) Leonard Judson S. (Acton MA) Cutler David N. (Nashua NH), Communications device for data processing system.
  22. Cummins Marty T. (Rochester MI), Computer software encryption apparatus.
  23. Satou Mitsugu,JPX ; Iwata Shunichi,JPX, Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory.
  24. Pai Hsin-Ying,TWX ; Hou Chien-Tzu, Computer system having a genetic code that cannot be directly accessed and a method of maintaining the same.
  25. Nakajima Atsushi (Fujisawa JPX) Nakagawa Yaoko (Hadano JPX), Computer system of virtual machines sharing a vector processor.
  26. Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Controlling access to multiple isolated memories in an isolated execution environment.
  27. Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Controlling access to multiple memory zones in an isolated execution environment.
  28. Curtis, Bryce Allen, Cross-platform program, system, and method having a global registry object for mapping registry equivalent functions in an OS/2 operating system environment.
  29. Best Robert M. (16016 9th Ave. NE. Seattle WA 98155), Crypto microprocessor for executing enciphered programs.
  30. Kaliski ; Jr. Burton S. (San Carlos CA), Cryptographic key escrow system having reduced vulnerability to harvesting attacks.
  31. Thomas Collins ; John Gregory ; Ralph Bestock, Cryptographic system.
  32. Herbert Howard C. ; Davis Derek L., Cryptographically protected paging subsystem.
  33. Guttag Karl M. (Houston TX), Data processing device formed on a single semiconductor substrate having secure memory.
  34. Kobayashi Souichi,JPX, Data processing system controlling bus access to an arbitrary sized memory area.
  35. Ugon Michel (Maurepas FRX), Data processing system including programming voltage inhibitor for an electrically erasable reprogrammable nonvolatile m.
  36. Matsuoka Michihiro (Sunto JPX) Ohba Yasumasa (Numazu JPX), Device for electrically detecting a liquid level.
  37. Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
  38. Morley Richard E. (Mason NH), Digital input/output system and method.
  39. England Paul ; DeTreville John D. ; Lampson Butler W., Digital rights management operating system.
  40. Lai Konrad K. (Aloha OR), Disabling tag bit recognition and allowing privileged operations to occur in an object-oriented memory protection mechan.
  41. Takahashi Richard J. (Phoenix AZ), Dual purpose security architecture with protected internal operating system.
  42. Davis, Derek L., Electronic system and method for controlling access through user authentication.
  43. Schneier Bruce ; Kelsey John M., Event auditing system.
  44. Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Executing isolated mode instructions in a secure system running in privilege rings.
  45. Nakamura Kouji,JPX, Exposure apparatus, output control method for energy source, laser device using the control method, and method of producing microdevice.
  46. Myntti Jon N. (Martinsville IN) Anderson Kirk P. (Phoenix AZ) Hosler Jay R. (Santa Cruz CA), Extended memory system and method.
  47. Akiyama Shin-Ichiro,JPX ; Yasuda Sadahiro,JPX ; Iizuka Yuichi,JPX ; Nishimoto Hiroaki,JPX ; Osada Yuuichi,JPX, Flash memory incorporating microcomputer having on-board writing function.
  48. Favor John G. ; Weber Frederick D., Flexible implementation of a system management mode (SMM) in a processor.
  49. Bernstein Peter Robert ; Shaw Andrew ; Thomas Royston Martin,GBX ; Veale Chris Allan ; Warner Peter,GBX ; Wolanin Donald John, Heterocyclic ketones.
  50. Merrill John W., Initializing and restarting operating systems.
  51. Dale E. Gulick, Interrupt driven isochronous task scheduler system.
  52. Kaplan Michael M. ; Ober Timothy ; Reed Peter, Kernel mode protection.
  53. Adams Phillip M. (Parowan UT) Holmstron Larry W. (Salt Lake City UT) Jacob Steve A. (South Weber UT) Powell Steven H. (Ogden UT) Condie Robert F. (Tuscon AZ) Culley Martin L. (Tuscon AZ), Kernels, description tables, and device drivers.
  54. Hazard Michel (Mareil Sur Mauldre FRX), Key protection device for smart cards.
  55. Birney Richard Eugene (Boca Raton FL) Davis Michael Ian (Boca Raton FL) Hood Robert Allen (Boca Raton FL), Key register controlled accessing system.
  56. England Paul ; DeTreville John D. ; Lampson Butler W., Loading and identifying a digital rights management operating system.
  57. Branigin Michael H. (Penllyn PA) Sherbert Edward G. (Plymouth Meeting PA) Krasucki ; Jr. Joseph F. (Downingtown PA), Main bus interface package.
  58. Yoshida Yukihiro (Ikoma JPX) Izaki Toru (Nara JPX) Maegawa Toshiyuki (Higashiosaka JPX) Tominaga Satoshi (Yamatokoriyama JPX), Memory clear system.
  59. Nozue Hiroshi,JPX ; Saito Mitsuo,JPX ; Maeda Kenichi,JPX ; Asano Shigehiro,JPX ; Okamoto Toshio,JPX ; Sungho Shin,JPX ; Segawa Hideo,JPX, Memory management and protection system for virtual memory in computer system.
  60. Johnson James Scott (Fort Worth TX) Short Tim (Duncanville TX) Intrater Gideon (Sunnyvale CA), Memory management circuit which provides simulated privilege levels.
  61. Barnett Philip C.,GBX, Memory management method and apparatus for partitioning homogeneous memory and restricting access of installed applications to predetermined memory ranges.
  62. Hackbarth Holden G. (Colorado Springs CO), Memory management unit for the MIL-STD 1750 bus.
  63. Chatterjee,Surojit; Srivastava,Alok K., Metadata format for hierarchical data storage on a raw storage device.
  64. Jablon David P. (Shrewsbury MA) Hanley Nora E. (Shrewsbury MA), Method and apparatus for assessing integrity of computer system software.
  65. Patarin Jacques,FRX, Method and apparatus for authenticating a data carrier intended to enable a transaction or access to a service or a loc.
  66. DeTreville, John, Method and apparatus for authenticating an open system application to a portable IC device.
  67. Chemin Francois (Plaisir FRX) Ugon Michel (Maurepas FRX), Method and apparatus for certifying services obtained using a portable carrier such as a memory card.
  68. Harold L. McFarland ; David R. Stiles ; Korbin S. Van Dyke ; Shrenik Mehta ; John Gregory Favor ; Dale R. Greenley ; Robert A. Cargnoni, Method and apparatus for debugging an integrated circuit.
  69. Dingwall Thomas J. ; Kumar Narasimha, Method and apparatus for embedding a real-time multi-tasking kernel in a non-real-time operating system.
  70. Helbig ; Sr. Walter A, Method and apparatus for enhancing computer system security.
  71. Ebrahim Zahir, Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU).
  72. Wildgrube Frank L. ; Albrecht Mark, Method and apparatus for increasing security against unauthorized write access to a protected memory.
  73. Miller David A. ; Jansen Kenneth A. ; Culley Paul R. ; Taylor Mark ; Izquierdo Javier F., Method and apparatus for independently resetting processors and cache controllers in multiple processor systems.
  74. Jasmin Ajanovic ; Serafin Garcia ; David J. Harriman, Method and apparatus for initializing a computer interface.
  75. Madany Peter W. ; Hamilton Graham ; Bishop Alan G., Method and apparatus for initializing a device.
  76. Arnold Todd Weston, Method and apparatus for protecting application data in secure storage areas.
  77. Kubala Jeffrey P. (Poughquag NY), Method and apparatus for providing a server function in a logically partitioned hardware machine.
  78. Van Dyke Korbin S., Method and apparatus for restricting memory access.
  79. Vu, Son Trung; Phan, Quang, Method and apparatus for secure processing of cryptographic keys.
  80. Cotichini Christian,CAX ; Cain Fraser,CAX ; Ashworth David G.,CAX ; Livingston Peter Michael Bruce,CAX ; Solymar Gabor,CAX ; Gardner Philip B.,CAX ; Woinoski Timothy S.,CAX, Method and apparatus to monitor and locate an electronic device using a secured intelligent agent.
  81. Bonola Thomas J., Method and appartus for emulating a peripheral device to allow device driver development before availability of the per.
  82. Luiz Fernando A. (Monte Sereno CA) Snyder Harlan C. (Saratoga CA) Sorg ; Jr. John H. (Los Gatos CA), Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system.
  83. Cromer, Daryl C.; Dayan, Richard A., Method and system for authenticated boot operations in a computer system of a networked computing environment.
  84. Sheu,John Te Jui; Bailey,David S.; Traut,Eric P.; Vega,Rene Antonio, Method and system for caching address translations from multiple address spaces in virtual machines.
  85. Kahle James Allan ; Loper Albert J. ; Mallick Soummya ; Ogden Aubrey Deene ; Sell John Victor, Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions w.
  86. Paul McGough, Method and system for performing secure electronic digital streaming.
  87. Barakat Simon (Andresy FRX), Method and system for suthenticating electronic memory cards.
  88. Saada Charles,FRX, Method and system for writing information in a data carrier making it possible to later certify the originality of this.
  89. Hazard Michel (Mareil/Mauldre FRX) Ugon Michel (Maurepas FRX), Method for authenticating an external authorizing datum by a portable object, such as a memory card.
  90. Melo Michael D. (Billerica MA), Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 8048.
  91. Hazard Michel (Mareil/Mauldre FRX), Method for certifying the authenticity of a datum exchanged between two devices connected locally or remotely by a trans.
  92. Ugon Michel (Maurepas FRX) Oisel Andr (Elancourt FRX), Method for checking the integrity of a program or data, and apparatus for implementing this method.
  93. Jean Bausch DE, Method for improving controllability in data processing system with address translation.
  94. Greenstein Paul Gregory ; Guyette Richard Roland ; Rodell John Ted, Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for.
  95. Davis Derek L. (Phoenix AZ), Method for providing a roving software license from one node to another node.
  96. Spilo Michael L. (248 E. 31st St. New York NY 10016), Method for providing protected mode services for device drivers and other resident software.
  97. Schwenk Joerg,DEX, Method for securing system protected by a key hierarchy.
  98. Ugon Michel (Maurepas FRX), Method for signature of an information processing file, and apparatus for implementing it.
  99. Patarin Jacques (Viroflay FRX), Method for the authentication of a portable object by an offline terminal, and apparatus for implementing the process.
  100. Bowman-Amuah, Michel K., Method for translating an object attribute converter in an information services patterns environment.
  101. Wakui Fujio (Hadano JPX) Onitsuka Takahiro (Hadano JPX) Nozaki Izumi (Zama JPX) Kuwabara Toshinori (Hadano JPX), Method of accessing multiple virtual address spaces and computer system.
  102. Tarik Slassi FR, Method of authenticating a personal code of a user of an integrated circuit card.
  103. Panwar Ramesh ; Chamdani Joseph I., Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency.
  104. Scalzi Casper A. (Poughkeepsie NY) Starke William J. (Austin TX), Method of using a target processor to execute programs of a source architecture that uses multiple address spaces.
  105. Rigal Vincent,FRX ; Koeberle Thierry,FRX, Method of writing information securely in a portable medium.
  106. Ganapathy Narayanan ; Stevens Luis F. ; Schimmel Curt F., Method, system and computer program product for dynamically allocating large memory pages of different sizes.
  107. Albrecht Mark ; Wildgrube Frank, Methods and apparatus for preventing unauthorized write access to a protected non-volatile storage.
  108. Ueno Masahiro (Hitachi JPX) Ono Kenichi (Hitachi JPX) Yamamoto Toshitaka (Hitachi JPX), Microcomputer with programmable ROM.
  109. Eugene Feng ; Gary Phillips, Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space.
  110. Phillips, Gary; Feng, Eugene, Microcontroller system having security circuitry to selectively lock portions of a program memory address space.
  111. Grimmer ; Jr. George G. ; Rhoades Michael W., Microcontroller with security logic circuit which prevents reading of internal memory by external program.
  112. Goetz John W. ; Mahin Stephen W. ; Bergkvist John J., Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set archi.
  113. Blomgren James S. (San Jose CA) Bracking Jimmy (San Jose CA) Richter David (San Jose CA) Spahn Francis (El Cerrito CA), Microprocessor with operation capture facility.
  114. Ganesan Ramanan V. ; Rao Vijay, Modem compatible method and apparatus for encrypting data that is transparent to software applications.
  115. Jose Alberto Tello CA, Modified computer motherboard security and identification system.
  116. Carlisle Adams CA; Michael J. Wiener CA, Multi-factor biometric authenticating device and method.
  117. Sudia Frank W. ; Freund Peter C. ; Huang Stuart T.F., Multi-step digital signature method and system.
  118. Hough Roger E. (Austin TX) Murray Robert E. (Kingston NY), Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals.
  119. Maeda Akira (Yokohama JPX), Multiprocessor system having mutual exclusion control function.
  120. McDonald, Michael F.; Arora, Sumeet; Chu, Mark, Mutual exclusion at the record level with priority inheritance for embedded systems using one semaphore.
  121. Reardon David C., Network security system allowing access and modification to a security subsystem after initial installation when a master token is in place.
  122. Trostle Jonathan, Networked workstation intrusion detection system.
  123. Attanasio Clement Richard (Peekskill NY) Belady Laszlo Antal (Yorktown Heights NY), Operating system authenticator.
  124. Davis Derek L., Optimized security functionality in an electronic system.
  125. Bhide Chandrashekhar W. ; Singh Jagdeep ; Oestreicher Don, Performance optimizations for computer networks utilizing HTTP.
  126. Derek L. Davis ; Howard C. Herbert, Platform and method for assuring integrity of trusted agent communications.
  127. Hostetter Mathew J., Pointer verification system and method.
  128. Neufeld E. David (Tomball TX), Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data trans.
  129. Oprescu Florin ; Teener Michael D., Power management system for computer device interconnection bus.
  130. Buer Mark Leonard, Power-on-reset logic with secure power down capability.
  131. Garney John I. (Aloha OR), Preservation of a computer system processing state in a mass storage device.
  132. Brands Stefanus A. (Ina Boudier-Bakkerlaan 143 III 3582 XW Utrecht NLX), Privacy-protected transfer of electronic information.
  133. Ugon Michel,FRX, Process for loading a protected storage zone of an information processing device, and associated device.
  134. Provanzano Salvatore R. (Melrose MA) Aldrich Wilbert H. (Winchester MA) D\Angelo Robert A. (Windham NH) Drottar Emil P. (Ipswich MA) Finnegan ; Jr. John J. (Hudson NH) Heom James (Bedford MA) Hill La, Programmable controller.
  135. Ashe Vincent,IEX, Protection for customer programs (EPROM).
  136. Robinson Paul T. (Arlington MA) Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA), Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces.
  137. John K. Gee ; David A. Greve ; David S. Hardin ; Allen P. Mass ; Michael H. Masters ; Nick M. Mykris ; Matthew M. Wilding, Real time processor capable of concurrently running multiple independent JAVA machines.
  138. Maytal Benjamin,ILX, Real-time task manager for a personal computer.
  139. John S. Yates, Jr. ; David L. Reese ; Korbin S. Van Dyke, Recording in a program execution profile references to a memory-mapped active device.
  140. Agesen,Ole; Sheldon,Jeffrey W., Restricting memory access to protect data when sharing a common address space.
  141. Davis Derek L. (Phoenix AZ), Roving software license for a hardware agent.
  142. Goire Christian (Les Clayes Sous Bois FRX) Sigaud Alain (Elancourt FRX) Moyal Eric (Paris FRX), Safeguarded remote loading of service programs by authorizing loading in protected memory zones in a terminal.
  143. Brands Stefanus A. (Ina Boudier-Bakkerlaan 143 (iii) XW Utrecht NLX 3582 ), Secret-key certificates.
  144. Davis Derek L., Secure BIOS.
  145. Davis Derek L., Secure boot.
  146. Browne Hendrik A., Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device.
  147. Abraham Dennis G. (Concord NC) Aden Steven G. (Cedar Park TX), Secure computer system having privileged and unprivileged memories.
  148. England, Paul; Lampson, Butler W., Secure execution of program code.
  149. Holtey Thomas O. (Newton MA) Wilson Peter J. (Leander TX), Secure memory card.
  150. Davis Derek L., Secure public digital watermark.
  151. Angelo Michael F., Secure software registration and integrity assessment in a computer system.
  152. Ugon Michel (Maurepas FRX), Security device prohibiting the function of an electronic data processing unit after a first cutoff of its electrical po.
  153. Fine Michael ; Rollins Randy, Security system for a computerized apparatus.
  154. Ashe Vincent,IEX, Security system protecting data with an encryption key.
  155. Nasu Hiroaki,JPX, Semiconductor device and electronic equipment having a non-volatile memory with a security function.
  156. Karkhanis Nitin Y. ; Noel Karen Lee, Sharing memory pages and page tables among computer processes.
  157. Jacks Steven Anthony ; McNeley Kevin John, Software for controlling a reliable backup memory.
  158. Serikawa Mitsuhiko,JPX ; Tagami Ryou,JPX ; Kawamura Akihisa,JPX ; Matsumoto Masaharu,JPX ; Oda Mikio,JPX ; Numazu Hiroko,JPX, Sound field and sound image control apparatus and method.
  159. Hanson Roger D. ; Sterrett Dale E., Straight through muffler with conically-ended output passage.
  160. Mark J. Foster ; Saifuddin T. Fakhruddin ; James L. Walker ; Matthew B. Mendelow ; Jiming Sun ; Rodman S. Brahman ; Michael P. Krau ; Brian D. Willoughby ; Michael D. Maddix ; Steven L. Belt, Suspend/resume capability for a protected mode microprocesser.
  161. Hudson Jerome D. ; Champagne Jean-Paul,FRX ; Galindo Mary A. ; Hickerson Cynthia M. K. ; Hickman Donna R. ; Lockhart Robert P. ; Saddler Nancy B. ; Stange Patricia A., System and method for accessing enterprise-wide resources by presenting to the resource a temporary credential.
  162. Davis Derek L., System and method for configuring and registering a cryptographic device.
  163. Wong-Insley Becky, System and method for cross-platform application level power management.
  164. Agesen, Ole; Subrahmanyam, Pratap; Devine, Scott W.; Rosenblum, Mendel; Bugnlon, Edouard, System and method for detecting access to shared structures and for maintaining coherence of derived structures in virtualized multiprocessor systems.
  165. Goldschlag David M. ; Stubblebine Stuart Gerald ; Syverson Paul F., System and method for electronic transactions.
  166. Derek L. Davis, System and method for ensuring integrity throughout post-processing.
  167. Angelo Michael F. ; Olarig Sompong P. ; Wooten David R. ; Driscoll Dan J., System and method for performing secure device communications in a peer-to-peer bus architecture.
  168. Ireton Mark A. ; Champagne Gerald ; Marler Corbett A., System and method for performing software patches in embedded systems.
  169. Paul C. Drews, System and method for verifying the integrity and authorization of software before execution in a local platform.
  170. Schneck Paul B. ; Abrams Marshall D., System for controlling access and distribution of digital property.
  171. Poisner, David L., System for detecting over-clocking uses a reference signal thereafter preventing over-clocking by reducing clock rate.
  172. Wolf Paul I. (San Diego CA) Ivans Norman B. (La Jolla CA), System for locating and anticipating data storage media failures.
  173. Poisner David I., System for providing first type access to register if processor in first mode and second type access to register if proc.
  174. Inoue Taro (Sagamihara JPX) Umeno Hidenori (Kanagawa JPX) Tanaka Shunji (Sagamihara JPX) Yamamoto Tadashi (Kanagawa JPX) Ohtsuki Toru (Hadano JPX), System for recovery from a virtual machine monitor failure with a continuous guest dispatched to a nonguest mode.
  175. Schimmel Curt F., System, method and computer program product for page sharing between fault-isolated cells in a distributed shared memory system.
  176. Little Wendell L. ; Curry Stephen M. ; Loomis Donald W., Systems and methods for protecting access to encrypted information.
  177. Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
  178. Nardone Joseph M. ; Mangold Richard T. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
  179. Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant player for scrambled contents.
  180. Kelly Edmund J. ; Cmelik Robert F. ; Wing Malcolm J., Translated memory protection apparatus for an advanced microprocessor.
  181. Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA) Robinson Paul T. (Arlington MA) Witek Richard T. (Littleton MA), Translation buffer for virtual machines with address space match.
  182. Guthery Scott B., Validating and certifying execution of a software program with a smart card.
  183. Hirosawa Toshio (Machida JPX) Kurihara Junichi (Hachioji JPX) Okumura Shigemi (Kiyose JPX) Uehara Tetsuzou (Nishitama JPX) Itoh Tsutomu (Hachioji JPX), Virtual computer system.
  184. Ogi Yoshifumi (Kawasaki JPX), Virtual computer system having input/output interrupt control of virtual machines.
  185. Onodera Osamu (Hadano JPX), Virtual machine I/O interrupt control method compares number of pending I/O interrupt conditions for non-running virtual.
  186. Bugnion Edouard ; Devine Scott W. ; Rosenblum Mendel, Virtual machine monitors for scalable multiprocessors.
  187. Inoue Taro (Kawasaki JPX) Umeno Hidenori (Kanagawa JPX) Ohtsuki Toru (Hadano JPX) Ogawa Kiyoshi (Yokohama JPX), Virtual machine system with vitual machine resetting store indicating that virtual machine processed interrupt without v.
  188. Seki Yukihiro (Yokohama JPX) Itoh Hiromichi (Yokohama JPX) Tsujioka Shigeo (Yokohama JPX), Virtual machine with hardware display controllers for base and target machines.
  189. Noel Karen Lee ; Harvey Michael Seward, Virtual memory allocation in a virtual address space having an inaccessible gap.
  190. Scott W. Devine ; Edouard Bugnion ; Mendel Rosenblum, Virtualization system including a virtual machine monitor for a computer with a segmented architecture.
  191. Di Santo Dennis E. (1620 Gobel Way Modesto CA 95358), Water dispenser with side by side filling-stations.

이 특허를 인용한 특허 (14)

  1. Heller, Lisa Cranton, Delaying purging of structures associated with address translation.
  2. Bradbury, Jonathan D.; Gschwind, Michael K.; Heller, Lisa Cranton; Jacobi, Christian; Osisek, Damian L.; Saporito, Anthony, Host page management using active guest page table indicators.
  3. Bradbury, Jonathan D.; Gschwind, Michael K., Host-based resetting of active use of guest page table indicators.
  4. Bradbury, Jonathan D.; Gschwind, Michael K., Host-based resetting of active use of guest page table indicators.
  5. Bradbury, Jonathan D.; Busaba, Fadi Y.; Heller, Lisa Cranton, Increasing the scope of local purges of structures associated with address translation.
  6. Bradbury, Jonathan D.; Gschwind, Michael K., Managing memory used to back address translation structures.
  7. Bradbury, Jonathan D.; Gschwind, Michael K., Marking page table/page status table entries to indicate memory used to back address translation structures.
  8. Bradbury, Jonathan D.; Gschwind, Michael K., Marking storage keys to indicate memory used to back address translation structures.
  9. Srinivasan, Kattiganehalli Y., Monitoring spin locks in virtual machines in a computing system environment.
  10. Bradbury, Jonathan D.; Jacobi, Christian; Saporito, Anthony, Reducing over-purging of structures associated with address translation.
  11. Bradbury, Jonathan D.; Jacobi, Christian; Saporito, Anthony, Reducing over-purging of structures associated with address translation using an array of tags.
  12. Bradbury, Jonathan D.; Heller, Lisa Cranton; Jacobi, Christian; Saporito, Anthony, Reducing purging of structures associated with address translation.
  13. Chen, Xiaoxin; Subrahmanyam, Pratap, System and method to enhance memory protection for programs in a virtual machine environment.
  14. Chen, Xiaoxin; Subrahmanyam, Pratap, System and method to enhance memory protection for programs in a virtual machine environment.
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