Method and apparatus for supporting address translation in a virtual machine environment
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-021/00
G06F-009/26
G06F-009/34
출원번호
UP-0154627
(2008-05-22)
등록번호
US-7836275
(2011-01-16)
발명자
/ 주소
Anderson, Andrew V.
Kägi, Alain
출원인 / 주소
Intel Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor & Zafman LLP
인용정보
피인용 횟수 :
14인용 특허 :
191
초록▼
In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based o
In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor (VMM) and attributes associated with entries in the shadow translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure.
대표청구항▼
What is claimed is: 1. A method comprising: creating a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and deriving metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hiera
What is claimed is: 1. A method comprising: creating a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and deriving metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hierarchy that are represented in the shadow PT hierarchy were modified, the metadata comprising an active entry list identifying mappings that map pages used by the guest operating system in forming the guest PT hierarchy, and one or more active directory lists identifying higher level mapping structures referencing a lower level structure through which the shadow PT hierarchy is to be accessed. 2. The method of claim 1 wherein: the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map PT pages and page directory (PD) pages from the guest PT hierarchy, and the one or more active directory lists include an active PD entry (PDE) list identifying PDEs in the shadow PT hierarchy, which point to PTs with the identified PTEs. 3. The method of claim 1 wherein: the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map any of page map level 4 (PML4) pages, page directory pointer (PDP) pages, page directory (PD) pages, and PT pages; and the one or more active directory lists include an active PD entry (PDE) list containing PDEs that reference a page with active PTE list entries, an active PDP entry (PDPE) list containing active PDPE entries which reference a PD with an active PDE list entry, and an active PML4E entry (PML4E) list containing entries which map a PDP with elements from the active PDPE list. 4. The method of claim 2 further comprising: tracking pages used by the guest operating system in forming the guest PT hierarchy; and tracking mappings to any Dynamic Random Access Memory (DRAM) backed page frame. 5. The method of claim 1 further comprising: identifying one or more large-size pages in the guest PT hierarchy; and creating a PT table in the shadow PT hierarchy for each of the one or more large-size pages. 6. The method of claim 1 further comprising: detecting a change in a structure of the guest PT hierarchy; and modifying the metadata to reflect the change. 7. The method of claim 1 wherein: content of the shadow PT hierarchy is used by a processor to cache address translations in the TLB. 8. An apparatus comprising: a memory to store instructions; a processor, coupled to the memory; and an address translator, executed from the memory by the processor to: create a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and derive metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hierarchy that are represented in the shadow PT hierarchy were modified, the metadata comprising an active entry list identifying mappings that map pages used by the guest operating system in forming the guest PT hierarchy, and one or more active directory lists identifying higher level mapping structures referencing a lower level structure through which the shadow PT hierarchy is to be accessed. 9. The apparatus of claim 8 wherein: the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map PT pages and page directory (PD) pages from the guest PT hierarchy, and the one or more active directory lists include an active PD entry (PDE) list identifying PDEs in the shadow PT hierarchy, which point to PTs with the identified PTEs. 10. The apparatus of claim 8 wherein: the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map any of page map level 4 (PML4) pages, page directory pointer (PDP) pages, page directory (PD) pages, and PT pages; and the one or more active directory lists include an active PD entry (PDE) list containing PDEs that reference a page with active PTE list entries, an active PDP entry (PDPE) list containing active PDPE entries which reference a PD with an active PDE list entry, and an active PML4E entry (PML4E) list containing entries which map a PDP with elements from the active PDPE list. 11. The apparatus of claim 9 wherein the address translator is further executed from the memory by the processor to: track pages used by the guest operating system in forming the guest PT hierarchy; and track mappings to any Dynamic Random Access Memory (DRAM) backed page frame. 12. The apparatus of claim 8 wherein the address translator is further executed from the memory by the processor to: identify one or more large-size pages in the guest PT hierarchy; and create a PT table in the shadow PT hierarchy for each of the one or more large-size pages. 13. The apparatus of claim 8 wherein the address translator is further executed from the memory by the processor to: detect a change in a structure of the guest PT hierarchy; and modify the metadata to reflect the change. 14. The apparatus of claim 8 wherein: content of the shadow PT hierarchy is used by the processor to cache address translations in the TLB. 15. A non-transient computer readable storage medium including instructions that, when executed by a processing system, cause the processing system to perform a method comprising: creating a shadow page table (PT) hierarchy based on a guest PT hierarchy used by a guest operating system for address translation operations; and deriving metadata from the shadow PT hierarchy to determine subsequently which entries of the guest PT hierarchy that are represented in the shadow PT hierarchy were modified, the metadata comprising an active entry list identifying mappings that map pages used by the guest operating system in forming the guest PT hierarchy, and one or more active director,,/lists identifying higher level mapping structures referencing a lower level structure through which the shadow PT hierarchy is to be accessed. 16. The computer readable storage medium of claim 15 wherein: the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map PT pages and page directory (PD) pages from the guest PT hierarchy, and the one or more active directory lists include an active PD entry (PDE) list identifying PDEs in the shadow PT hierarchy, which point to PTs with the identified PTEs. 17. The computer readable storage medium of claim 15 wherein: the active entry list is an active PT entry (PTE) list identifying PTEs in the shadow PT hierarchy, which map any of page map level 4 (PML4) pages, page directory pointer (PDP) pages, page directory (PD) pages, and PT pages; and the one or more active directory lists include an active PD entry (PDE) list containing PDEs that reference a page with active PTE list entries, an active PDP entry (PDPE) list containing active PDPE entries which reference a PD with an active PDE list entry, and an active PML4E entry (PML4E) list containing entries which map a PDP with elements from the active PDPE list. 18. The computer readable storage medium of claim 16, wherein the method further comprises: tracking pages used by the guest operating system in forming the guest PT hierarchy; and tracking mappings to any Dynamic Random Access Memory (DRAM) backed page frame. 19. The computer readable storage medium of claim 15, wherein the method further comprises: identifying one or more large-size pages in the guest PT hierarchy; and creating a PT table in the shadow PT hierarchy for each of the one or more large-size pages. 20. The computer readable storage medium of claim 15, wherein the method further comprises: detecting a change in a structure of the guest PT hierarchy; and modifying the metadata to reflect the change. 21. The computer readable storage medium of claim 15 wherein: content of the shadow PT hierarchy is used by a processor to cache address translations in the TLB.
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이 특허에 인용된 특허 (191)
Ryba Edward G. (Milpitas CA) Lipman Peter H. (Cupertino CA) Connell Jefferson J. (Cupertino CA) Weiss David (Palo Alto CA), Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB).
Gannon Patrick M. (Poughkeepsie NY) Gum Peter H. (Poughkeepsie NY) Hough Roger E. (Highland NY) Murray Robert E. (Woodstock NY), Apparatus and method for TLB purge reduction in a multi-level machine system.
Bealkowski Richard (Delray Beach FL) Blackledge ; Jr. John W. (Boca Raton FL) Cronk Doyle S. (Boca Raton FL) Dayan Richard A. (Boca Raton FL) Dixon Jerry D. (Boca Raton FL) Kinnear Scott G. (Boca Rat, Apparatus and method for preventing unauthorized access to BIOS in a personal computer system.
Brelsford David P. (Hyde Park NY) Cutler Melvin M. (Los Angeles CA) Lafitte Jean-Louis (Moens NY FRX) Gdaniec Joseph M. (Hyde Park NY) Osisek Damian L. (Vestal NY) Plambeck Kenneth E. (Poughkeepsie N, Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virt.
Heller Andrew R. (Morgan Hill CA) Worley ; Jr. William S. (Endicott NY), Authorization mechanism for transfer of program control or data between different address spaces having different storag.
Ermolovich Thomas R. (Lexington MA) Stewart Robert E. (Stow MA) Leonard Judson S. (Acton MA) Cutler David N. (Nashua NH), Communications device for data processing system.
Satou Mitsugu,JPX ; Iwata Shunichi,JPX, Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory.
Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Controlling access to multiple isolated memories in an isolated execution environment.
Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Controlling access to multiple memory zones in an isolated execution environment.
Curtis, Bryce Allen, Cross-platform program, system, and method having a global registry object for mapping registry equivalent functions in an OS/2 operating system environment.
Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
Ellison, Carl M.; Golliver, Roger A.; Herbert, Howard C.; Lin, Derrick C.; McKeen, Francis X.; Neiger, Gilbert; Reneris, Ken; Sutton, James A.; Thakkar, Shreekant S.; Mittal, Millind, Executing isolated mode instructions in a secure system running in privilege rings.
Nakamura Kouji,JPX, Exposure apparatus, output control method for energy source, laser device using the control method, and method of producing microdevice.
Adams Phillip M. (Parowan UT) Holmstron Larry W. (Salt Lake City UT) Jacob Steve A. (South Weber UT) Powell Steven H. (Ogden UT) Condie Robert F. (Tuscon AZ) Culley Martin L. (Tuscon AZ), Kernels, description tables, and device drivers.
Johnson James Scott (Fort Worth TX) Short Tim (Duncanville TX) Intrater Gideon (Sunnyvale CA), Memory management circuit which provides simulated privilege levels.
Barnett Philip C.,GBX, Memory management method and apparatus for partitioning homogeneous memory and restricting access of installed applications to predetermined memory ranges.
Chemin Francois (Plaisir FRX) Ugon Michel (Maurepas FRX), Method and apparatus for certifying services obtained using a portable carrier such as a memory card.
Harold L. McFarland ; David R. Stiles ; Korbin S. Van Dyke ; Shrenik Mehta ; John Gregory Favor ; Dale R. Greenley ; Robert A. Cargnoni, Method and apparatus for debugging an integrated circuit.
Miller David A. ; Jansen Kenneth A. ; Culley Paul R. ; Taylor Mark ; Izquierdo Javier F., Method and apparatus for independently resetting processors and cache controllers in multiple processor systems.
Cotichini Christian,CAX ; Cain Fraser,CAX ; Ashworth David G.,CAX ; Livingston Peter Michael Bruce,CAX ; Solymar Gabor,CAX ; Gardner Philip B.,CAX ; Woinoski Timothy S.,CAX, Method and apparatus to monitor and locate an electronic device using a secured intelligent agent.
Luiz Fernando A. (Monte Sereno CA) Snyder Harlan C. (Saratoga CA) Sorg ; Jr. John H. (Los Gatos CA), Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system.
Sheu,John Te Jui; Bailey,David S.; Traut,Eric P.; Vega,Rene Antonio, Method and system for caching address translations from multiple address spaces in virtual machines.
Kahle James Allan ; Loper Albert J. ; Mallick Soummya ; Ogden Aubrey Deene ; Sell John Victor, Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions w.
Hazard Michel (Mareil/Mauldre FRX) Ugon Michel (Maurepas FRX), Method for authenticating an external authorizing datum by a portable object, such as a memory card.
Melo Michael D. (Billerica MA), Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 8048.
Hazard Michel (Mareil/Mauldre FRX), Method for certifying the authenticity of a datum exchanged between two devices connected locally or remotely by a trans.
Ugon Michel (Maurepas FRX) Oisel Andr (Elancourt FRX), Method for checking the integrity of a program or data, and apparatus for implementing this method.
Greenstein Paul Gregory ; Guyette Richard Roland ; Rodell John Ted, Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for.
Panwar Ramesh ; Chamdani Joseph I., Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency.
Scalzi Casper A. (Poughkeepsie NY) Starke William J. (Austin TX), Method of using a target processor to execute programs of a source architecture that uses multiple address spaces.
Ganapathy Narayanan ; Stevens Luis F. ; Schimmel Curt F., Method, system and computer program product for dynamically allocating large memory pages of different sizes.
Eugene Feng ; Gary Phillips, Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space.
Grimmer ; Jr. George G. ; Rhoades Michael W., Microcontroller with security logic circuit which prevents reading of internal memory by external program.
Goetz John W. ; Mahin Stephen W. ; Bergkvist John J., Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set archi.
Blomgren James S. (San Jose CA) Bracking Jimmy (San Jose CA) Richter David (San Jose CA) Spahn Francis (El Cerrito CA), Microprocessor with operation capture facility.
Hough Roger E. (Austin TX) Murray Robert E. (Kingston NY), Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals.
McDonald, Michael F.; Arora, Sumeet; Chu, Mark, Mutual exclusion at the record level with priority inheritance for embedded systems using one semaphore.
Reardon David C., Network security system allowing access and modification to a security subsystem after initial installation when a master token is in place.
Neufeld E. David (Tomball TX), Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data trans.
Provanzano Salvatore R. (Melrose MA) Aldrich Wilbert H. (Winchester MA) D\Angelo Robert A. (Windham NH) Drottar Emil P. (Ipswich MA) Finnegan ; Jr. John J. (Hudson NH) Heom James (Bedford MA) Hill La, Programmable controller.
Robinson Paul T. (Arlington MA) Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA), Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces.
John K. Gee ; David A. Greve ; David S. Hardin ; Allen P. Mass ; Michael H. Masters ; Nick M. Mykris ; Matthew M. Wilding, Real time processor capable of concurrently running multiple independent JAVA machines.
Goire Christian (Les Clayes Sous Bois FRX) Sigaud Alain (Elancourt FRX) Moyal Eric (Paris FRX), Safeguarded remote loading of service programs by authorizing loading in protected memory zones in a terminal.
Browne Hendrik A., Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device.
Mark J. Foster ; Saifuddin T. Fakhruddin ; James L. Walker ; Matthew B. Mendelow ; Jiming Sun ; Rodman S. Brahman ; Michael P. Krau ; Brian D. Willoughby ; Michael D. Maddix ; Steven L. Belt, Suspend/resume capability for a protected mode microprocesser.
Hudson Jerome D. ; Champagne Jean-Paul,FRX ; Galindo Mary A. ; Hickerson Cynthia M. K. ; Hickman Donna R. ; Lockhart Robert P. ; Saddler Nancy B. ; Stange Patricia A., System and method for accessing enterprise-wide resources by presenting to the resource a temporary credential.
Agesen, Ole; Subrahmanyam, Pratap; Devine, Scott W.; Rosenblum, Mendel; Bugnlon, Edouard, System and method for detecting access to shared structures and for maintaining coherence of derived structures in virtualized multiprocessor systems.
Angelo Michael F. ; Olarig Sompong P. ; Wooten David R. ; Driscoll Dan J., System and method for performing secure device communications in a peer-to-peer bus architecture.
Inoue Taro (Sagamihara JPX) Umeno Hidenori (Kanagawa JPX) Tanaka Shunji (Sagamihara JPX) Yamamoto Tadashi (Kanagawa JPX) Ohtsuki Toru (Hadano JPX), System for recovery from a virtual machine monitor failure with a continuous guest dispatched to a nonguest mode.
Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
Nardone Joseph M. ; Mangold Richard T. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant methods and apparatus.
Nardone Joseph M. ; Mangold Richard P. ; Pfotenhauer Jody L. ; Shippy Keith L. ; Aucsmith David W. ; Maliszewski Richard L. ; Graunke Gary L., Tamper resistant player for scrambled contents.
Mason Andrew H. (Hollis NH) Hall Judith S. (Sudbury MA) Robinson Paul T. (Arlington MA) Witek Richard T. (Littleton MA), Translation buffer for virtual machines with address space match.
Scott W. Devine ; Edouard Bugnion ; Mendel Rosenblum, Virtualization system including a virtual machine monitor for a computer with a segmented architecture.
Bradbury, Jonathan D.; Gschwind, Michael K.; Heller, Lisa Cranton; Jacobi, Christian; Osisek, Damian L.; Saporito, Anthony, Host page management using active guest page table indicators.
Bradbury, Jonathan D.; Gschwind, Michael K., Marking page table/page status table entries to indicate memory used to back address translation structures.
Bradbury, Jonathan D.; Jacobi, Christian; Saporito, Anthony, Reducing over-purging of structures associated with address translation using an array of tags.
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