Process for collective manufacturing of small volume high precision membranes and cavities
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/46
H01L-021/302
H01L-021/461
출원번호
UP-0298894
(2007-04-26)
등록번호
US-7838393
(2011-01-22)
우선권정보
FR-06 51511(2006-04-28)
국제출원번호
PCT/EP2007/054106
(2007-04-26)
§371/§102 date
20081028
(20081028)
국제공개번호
WO07/128705
(2007-11-15)
발명자
/ 주소
Collet, Joel
Nicolas, Stephane
Pisella, Christian
출원인 / 주소
Tronic's Microsystems
대리인 / 주소
Nixon Peabody LLP
인용정보
피인용 횟수 :
1인용 특허 :
3
초록▼
The invention relates to a process for collective manufacturing of cavities and/or membranes (24), with a given thickness d, in a wafer said to be a semiconductor on insulator layer, comprising at least one semiconducting surface layer with a thickness d on an insulating layer, this insulating layer
The invention relates to a process for collective manufacturing of cavities and/or membranes (24), with a given thickness d, in a wafer said to be a semiconductor on insulator layer, comprising at least one semiconducting surface layer with a thickness d on an insulating layer, this insulating layer itself being supported on a substrate, this process comprising: etching of the semiconducting surface layer with thickness d, the insulating layer forming a stop layer, to form said cavities and/or membranes in the surface layer.
대표청구항▼
The invention claimed is: 1. Process for making a closed or semi-closed volume, involving a first and second semiconductor on insulator type wafers, each of these wafers comprising at least one semiconducting surface layer on an electrically insulating layer, this insulating layer being itself supp
The invention claimed is: 1. Process for making a closed or semi-closed volume, involving a first and second semiconductor on insulator type wafers, each of these wafers comprising at least one semiconducting surface layer on an electrically insulating layer, this insulating layer being itself supported on a substrate, this process comprising: in the first semiconductor on insulator type wafer, etching of the semiconducting surface layer, the insulating layer forming an etch-stop layer, wherein a portion of the insulating layer in contact with the substrate is not removed, to make at least one cavity, in the second semiconductor on insulator type wafer, etching of the semiconducting surface layer, the insulating layer forming an etch-stop layer, wherein a portion of the insulating layer in contact with the substrate is not removed, to make at least one membrane, etching of the substrate and the electrically insulating layer of the first and second wafers, alignment of said two wafers, assembly of said two wafers, so as to position said membrane against said cavity, said membrane acting as a valve for said cavity, a thinning step performed on at least one of the two wafers, after assembly of these two wafers. 2. Process according to claim 1, said wafers being SOI wafers. 3. Process according to claim 2, said wafers being EPI-SOI type wafers, obtained by epitaxy. 4. Process according to claim 1, one of said wafers being a double SOI wafer. 5. Process according to claim 1, also comprising positioning of a mask on or above the surface layer of said first and/or second wafer, before etching. 6. Process for manufacturing a micro valve, comprising: the formation of at least one seat of said micro-valve in a semiconducting surface layer of a first semiconductor on insulator wafer, this insulating layer being itself supported on a substrate, by etching of said semiconducting surface layer, the insulating layer forming an etch-stop layer, wherein a portion of the insulating layer in contact with the substrate is not removed, the formation of at least one membrane of said micro-valve in a semiconducting surface layer of a second semiconductor on insulator wafer, this insulating layer being itself supported on a substrate, by etching of said semiconducting surface layer, the insulating layer forming an etch-stop layer, wherein a portion of the insulating layer in contact with the substrate is not removed, etching of the substrate and the electrically insulating layer of the first and second wafers, assembly of said first and second wafers, so as to position the membrane on the seat. 7. Process according to claim 6, also comprising: the formation of at least one membrane in at least said first wafer, and at least one seat in the surface layer of the semiconducting material of said first wafer, and at least one seat and at least one membrane in the surface layer of semiconducting material of said second wafer, assembly of said first and second wafers, forming at least two micro-valves. 8. Process according to claim 1, further comprising a step to make a cover in a third wafer, and a step to assemble this cover with said first and second wafers. 9. Process according to claim 8, said third wafer being an SOI wafer. 10. Process according to claim 8, said cover comprising at least one membrane. 11. Process according to claim 10, also comprising the formation of activation means of said at least one membrane, for example piezoelectric or electrostatic or magnetic or pneumatic activation means. 12. Process according to claim 10, said at least one membrane being delimited by two cavities made in the third wafer. 13. Process according to claim 1, said two wafers being assembled by direct or indirect bonding, with or without the addition of intermediate material. 14. Process according to claim 1, said two wafers being assembled by molecular bonding. 15. Process according to claim 1, the semiconducting surface layer of said first and/or second wafers being made of silicon (Si) or of SiGe. 16. Process according to claim 1, the insulating layer of said first and/or second wafers being an oxide layer or a nitride layer.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (3)
Reinhard Linnemann DE; Martin Richter DE; Stefan Kluge DE; Peter Woias DE, Method for producing a micromembrane pump body.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.