초록 ▼

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.)

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

대표청구항 ▼

The invention claimed is: 1. An integrated circuit, comprising: a plurality of regions arranged in a multi-dimensional interconnection network having a plurality of input terminals and at least one output terminal, wherein: a first subset of conductors along a first dimension of the multi-dimension

The invention claimed is: 1. An integrated circuit, comprising: a plurality of regions arranged in a multi-dimensional interconnection network having a plurality of input terminals and at least one output terminal, wherein: a first subset of conductors along a first dimension of the multi-dimensional interconnection network is configured to form part of a first normal speed portion of the interconnection network; and a second subset of conductors along the first dimension of the multi-dimensional interconnection network is configured to form part of a second high-speed portion of the interconnection network, wherein the conductors of the second high-speed portion is programmable to directly connect the output of any of the regions to at least one of the input terminals of substantially any of the adjacent regions in the first dimension. 2. The integrated circuit of claim 1, wherein the second subset of conductors is programmable to optionally make at least part of a connection between any of the regions and at least one of the input terminals of substantially any of the regions. 3. The integrated circuit of claim 1, wherein the adjacent regions include at least one region extending horizontally adjacent to the region that has its output terminal being connected to the subset. 4. The integrated circuit of claim 1, wherein the adjacent regions include at least one region extending vertically adjacent to the region that has its output terminal being connected to the subset. 5. The integrated circuit of claim 2, wherein the second subset of conductors is configured to optionally make at least part of a connection between the output terminal of any of the regions and at least one of the input terminals of substantially any of regions by providing signal routing which is alternative to at least part of routing for the same connection through the first subset of conductors, the alternative routing through the second high-speed portion being substantially faster than routing through the first normal-speed portion to which the alternative routing is alternative. 6. The integrated circuit of claim 1, wherein the regions are disposed on the integrated circuit in groups associated with and extending along the first dimension. 7. The integrated circuit of claim 6, further comprising a third subset of conductors dispersed on the integrated circuit in groups associated with and extending along a second dimension of the multi-dimensional interconnection network, and programmable connectors configured to selectively interconnect the first and second sets of conductors with the third set of conductors. 8. The integrated circuit of claim 7, wherein a first subset of the third subset of conductors is configured to form part of the first normal-speed portion of the interconnection network, and a second subset of the third subset of conductors is configured to form part of the second high-speed portion of the interconnection network. 9. The integrated circuit of claim 8, wherein the first subset in each of the groups includes more of the conductors in that group than the second subset of that group includes. 10. The integrated circuit of claim 9, wherein the first subset in each of the groups includes in the range from about 67% to about 80% of the conductors in that group. 11. The integrated circuit of claim 8, wherein the programmable connectors include a first subset of the connectors that are configured to selectively interconnect conductors in the first and second dimensions in the first subsets of the conductors but not conductors in the second subsets of the conductors. 12. The integrated circuit of claim 8, wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect conductors in the second subset of the conductors but not conductors in the first subsets of the conductors. 13. The integrated circuit of claim 1, wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect conductors in the second subset of the conductors but not conductors in the first subsets of the conductors. 14. The integrated circuit of claim 13, wherein each of the programmable connectors includes a signal driver, and wherein the signal drivers of the second subset of the connectors are larger and more powerful than the signal drivers of the first subset of the connectors. 15. The integrated circuit of claim 8, wherein the conductors of the second subset of the conductors in each of the groups are wider than the conductors in the first subset of the conductors in that group. 16. The integrated circuit of claim 8, wherein the conductors of the second subset of conductors in each of the groups are spaced more widely from other conductors than the conductors in the first subset of the conductors in that group. 17. The integrated circuit of claim 8, further comprising programmable circuitry configured to apply signals from at least some of the interconnection conductors associated with each of the regions to at least one input terminal of that region, the programmable circuitry including connection paths that are more direct for signals from conductors in the second subset of the conductors associated with that region than from signals from conductors in the first subset of conductors associated with that region. 18. The integrated circuit of claim 8, further comprising a plurality of high-speed regional interconnection conductors associated with and extending along each of a plurality of subsets of the adjacent regions in at least one of the first dimension and the second dimension. 19. The integrated circuit of claim 18, wherein each of the high-speed regional interconnection conductors is configured for programmable connection to the output terminal of one of the associated regions that is approximately centered amid the multiple adjacent regions associated with that high-speed regional interconnection conductor. 20. The integrated circuit of claim 19, wherein each of the high-speed regional interconnection conductors associated with each region is programmably connectable to at least one input terminal of substantially any of the regions associated with that high-speed regional interconnection conductor.