IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0716545
(2007-03-08)
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등록번호 |
US-7844862
(2011-01-31)
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발명자
/ 주소 |
- Grove, Daniel Dwight
- Posva, Ivan
- Choquette, Jack H.
- Click, Jr., Cliff N.
- Gee, Jeffrey
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
7 인용 특허 :
7 |
초록
Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous ordering operation.
대표청구항
▼
What is claimed is: 1. A method of detecting a race condition, comprising: receiving an indication of a store operation to a memory address; storing an identifier of the memory address; and using the identifier to detect an occurrence of a memory operation that is not associated with a previous ord
What is claimed is: 1. A method of detecting a race condition, comprising: receiving an indication of a store operation to a memory address; storing an identifier of the memory address; and using the identifier to detect an occurrence of a memory operation that is not associated with a previous ordering operation, including using the identifier of the memory address to search a global data structure associated with a plurality of processors; wherein: a search result of the global data structure can be used to identify a private data structure associated with at least one processor; and detecting the memory operation includes using the identifier of the memory address to search the private data structure. 2. A method as recited in claim 1, wherein the memory operation includes one or more of the following: a store operation to the memory address, and a load operation from the memory address. 3. A method as recited in claim 1, wherein using the identifier to detect the memory operation occurrence includes determining that an ordering operation has been omitted. 4. A method as recited in claim 1, wherein using the identifier to detect the memory operation occurrence includes performing one or more of the following: trapping the memory operation, replacing the memory operation, and running the memory operation in a simulator. 5. A method as recited in claim 1, wherein the ordering operation includes one or more of the following: a fence operation, a barrier operation, and a compare and swap operation. 6. A method as recited in claim 1, wherein using the identifier to detect the memory operation occurrence includes displaying or logging information of the memory operation. 7. A method as recited in claim 6, wherein the information of the memory operation includes one or more of the following: the memory address, an identifier of a processor performing the memory operation, and an identifier of a location within a program. 8. A method as recited in claim 1, wherein detecting the memory operation occurrence allows a user to view, identify, or correct an undesired race condition caused by the memory operation. 9. A method as recited in claim 1, further comprising associating and storing with the identifier of the memory address one or more of the following: an identifier of a processor associated with the memory operation, a program counter, an identifier of a location within a program, a stack location, a stack trace, and a function name. 10. A method as recited in claim 1, wherein using the identifier to detect the memory operation occurrence includes determining that the memory operation occurrence is associated with a different processor from a processor associated with the store operation. 11. A method as recited in claim 1, wherein the identifier of the memory address includes at least a portion of the memory address. 12. A method as recited in claim 1, wherein the store operation is associated with a first processor, and the using the identifier to detect the memory operation occurrence includes determining whether a store operation of a second processor has stored to the memory address after a latest ordering operation has been performed. 13. A method as recited in claim 1, wherein the store operation is associated with a first processor, and the using the identifier to detect the memory operation occurrence includes determining whether a load operation of a second processor has loaded from the memory address after a latest ordering operation has been performed. 14. A method as recited in claim 1, wherein storing the identifier of the memory address includes storing the identifier in a data structure associated with a single processor. 15. A method as recited in claim 14, wherein the identifier of the memory address is stored in a data structure associated with a plurality of processors. 16. A method as recited in claim 1, wherein storing the identifier of the Memory address includes storing the identifier in a data structure associated with a plurality of processors. 17. A method as recited in claim 16, wherein the data structure includes an unlocked hash table. 18. A method as recited in claim 16, wherein the identifier of the memory address is stored with a generation identifier that can be used to determine whether the memory operation is performed after the ordering operation. 19. A method as recited in claim 1, wherein a search result of the global data structure indicates a memory address that is potentially associated with a race condition. 20. A method as recited in claim 1, wherein using the identifier to detect the memory operation occurrence includes using one or more predetermined criteria to determine the memory operation is not associated with a benign race condition. 21. A method as recited in claim 1, wherein the ordering operation orders memory operations such that a store operation, if any, of a processor occurring before the ordering operation is visible to other processors before any memory operation occurring after the ordering operation. 22. A method as recited in claim 1, wherein performing the ordering operation includes removing the stored identifier of the memory address. 23. A method as recited in claim 1, wherein the performing the ordering operation includes updating a generation reference identifier that can be used to determine whether the memory operation is performed after the ordering operation. 24. A system for detecting a race condition, comprising: a processor; and a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to: receive an indication of a store operation to a memory address, store an identifier of the memory address, and use the identifier to detect an occurrence of a memory operation that is not associated with a previous ordering operation; wherein: using the identifier to detect the memory operation occurrence includes using the identifier of the memory address to search a global data structure associated with a plurality of processors; a search result of the global data structure can be used to identify a private data structure associated with at least one processor; and detecting the memory operation includes using the identifier of the memory address to search the private data structure. 25. A computer program product for detecting a race condition, the computer program product being embodied in a computer readable medium and comprising computer instructions for: receiving an indication of a store operation to a memory address; storing an identifier of the memory address; and using the identifier to detect an occurrence of a memory operation that is not associated with a previous ordering operation, including using the identifier of the memory address to search a global data structure associated with a plurality of processors; wherein: a search result of the global data structure can be used to identify a private data structure associated with at least one processor; and detecting the memory operation includes using the identifier of the memory address to search the private data structure.
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