IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
UP-0433331
(2006-05-12)
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등록번호 |
US-7853634
(2011-02-10)
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발명자
/ 주소 |
- Simkins, James M.
- Wong, Jennifer
- New, Bernard J.
- Ching, Alvin Y.
- Thendean, John M.
- Wong, Anna Wing Wah
- Vadi, Vasisht Mantra
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
9 인용 특허 :
140 |
초록
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An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein th
An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.
대표청구항
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What is claimed is: 1. An Integrated circuit(IC) having a single-instruction-multiple-data (SIMD) circuit, the SIMD circuit comprising: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit coupled to the plurality of multiplexers and controlled by a second opcode;
What is claimed is: 1. An Integrated circuit(IC) having a single-instruction-multiple-data (SIMD) circuit, the SIMD circuit comprising: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the arithmetic logic unit comprises a plurality of adders, the plurality of adders controlled by at least some bits of the second opcode, wherein a first adder of the plurality of adders adds a first plurality of input bits to produce first summation bits and a first carry bit, wherein a second adder of the plurality of adders adds a second plurality of input bits to produce second summation bits and a second carry bit, and wherein a third adder of the plurality of adders adds a third plurality of input bits to produce third summation bits and a third carry bit, and the first, second, and third adders operate concurrently with each other. 2. The IC of claim 1 wherein a fourth adder of the plurality of adders adds a fourth plurality of input bits to produce fourth summation bits and a fourth carry bit, and wherein the first, second, third, and fourth adders operate concurrently with each other. 3. The IC of claim 1 wherein the plurality of adders comprises carry look ahead adders and wherein the arithmetic logic unit further comprises a plurality of bitwise adders coupled to the carry look ahead adders, the plurality of bitwise adders configured to add three input data sets from the plurality of multiplexers and produce a sum set of bits and a carry set of bits. 4. The IC of claim 3 wherein first carry look ahead adders associated with the first adder add together a first subset of the sum set of bits and a first subset of the carry set of bits to produce the first summation bits and the first carry bit. 5. The IC of claim 4 wherein second carry look ahead adders associated with the second adder of the plurality of adders add together a second subset of the sum set of bits and a second subset of the carry set of bits to produce the second summation bits and the second carry bit. 6. An integrated circuit (IC) having a single instruction multiple data (SIMD) circuit, the SIMD circuit comprising: first and second multiplexers coupled to a first plurality of arithmetic unit elements, the function of the plurality of arithmetic unit elements determined by a first instruction; an output of a first configurable multiplexer comprising a first plurality of data slices; an output of a second configurable multiplexer comprising a second plurality of data slices; a first output slice of a first arithmetic unit element of the first plurality of arithmetic unit elements, the first output slice produced from at least inputting a first slice from the first plurality of data slices and a first slice from the second plurality of data slices into the first arithmetic unit element; and a second output slice of a second arithmetic unit element of the first plurality of arithmetic unit elements, the second output slice produced from at least inputting a second slice from the first plurality of data slices and a second slice from the second plurality of data slices into the second arithmetic unit element. 7. The integrated circuit (IC) of claim 6 wherein the first and second multiplexers are programmed by a second instruction. 8. The integrated circuit (IC) of claim 6 wherein the first arithmetic unit element outputs a carry out in response to at least adding together the first slice from the first plurality of data slices and the first slice from the second plurality of data slices. 9. The integrated circuit (IC) of claim 6 having another SIMD circuit coupled to the SIMD circuit, the another SIMD circuit comprising: third and fourth multiplexers coupled to a second plurality of arithmetic unit elements; an output of a third configurable multiplexer comprising a third plurality of data slices; and an output of a fourth configurable multiplexer comprising a fourth plurality of data slices, the fourth plurality of data slices comprising the first output slice of the first arithmetic unit element and the second output slice of the second arithmetic unit element. 10. The IC of claim 9 further comprising; a third output slice of a third arithmetic unit element of the second plurality of arithmetic unit elements, the third output slice produced from at least inputting a first slice from the third plurality of data slices and a first slice from the fourth plurality of data slices into the third arithmetic unit element; and a fourth output slice of a fourth arithmetic logic unit element of the second plurality of arithmetic unit elements, the fourth output slice produced from at least inputting a second slice from the third plurality of data slices and a second slice from the fourth plurality of data slices into the fourth arithmetic unit element. 11. The IC of claim 9 wherein the second plurality of arithmetic unit elements is controlled by a second instruction and combined with the first plurality of arithmetic unit elements controlled by the first instruction forms a multiple-instruction-multiple-data (MIMD) unit. 12. An integrated circuit (IC) having a single instruction multiple data circuit comprising: a first plurality of multiplexers receiving a first set, second set, and third set of input data bits, the first plurality of multiplexers controlled by at least part of a first opcode; a bitwise adder coupled to the first plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; a carry look ahead adder coupled to the bitwise adder for adding together the sum set of bits and the carry set of bits to produce a summation set of bits and a carry-out set of bits; wherein the carry look ahead adder comprises a plurality of carry look ahead circuit elements formed into K groups, where K is a positive integer and where each of the K groups, produces a subset of the summation set of bits and a subset of the carry-out set of bits; and a second plurality of multiplexers coupled to the K groups and controlled by at least part of a second opcode. 13. The IC of claim 12 wherein a carry look ahead circuit element of the plurality of carry look ahead circuit elements in a first group of the K groups comprises: a first m-bit carry look ahead adder adding together a zero carry-in, a m-bit subset of the sum set of bits, and a m-bit output of carry bits from a single instruction multiple data (SIMD) multiplexer, where m is a positive number; a second m-bit carry look ahead adder adding together a one carry-in, the m-bit subset of the sum set of bits, and the m-bit output of carry bits from the SIMD multiplexer; and a multiplexer coupled to the first and second m-bit carry look ahead adders. 14. The IC of claim 13 wherein a second carry look ahead circuit element of the plurality of carry look ahead circuit elements in the first group of the K groups comprises: a third m-bit carry look ahead adder adding together a zero carry-in, a second m-bit subset of the sum set of bits plus one zero bit, and a second m+1-bit subset of the carry set of bits; a fourth m-bit carry look ahead adder adding together a one carry-in, the m-bit subset of the sum set of bits plus one zero bit, and the m+1-bit subset of the carry set of bits; and a second multiplexer coupled to the third and fourth m-bit carry look ahead adders. 15. The IC of claim 12 further comprising: a first group of the K groups of carry look ahead adders configured to produce a first subset of the summation set of bits and a first bit of the carry-out set of bits; a first multiplexer of the second plurality of multiplexers receiving the first subset of the summation set of bits and inverting the first subset depending upon a first bit of the second opcode; and a second multiplexer of the second plurality of multiplexers receiving the first bit of the carry-out set of bits and inverting the first bit depending upon an output of a logical AND of the first bit of the second opcode with a second bit of the second opcode. 16. The IC of claim 15 further comprising: a first register coupled to the first multiplexer; and a second register coupled to the second multiplexer. 17. The IC of claim 15 further comprising: a second group of the K groups of carry look ahead adders configured to produce a second subset of the summation set of bits and a second bit and a third bit of the carry-out set of bits; a third multiplexer of the second plurality of multiplexers receiving the second subset of the summation set of bits and inverting the second subset depending upon the first bit of the second opcode; and a fourth multiplexer of the second plurality of multiplexers receiving the second bit of the carry-out set of bits and inverting the second bit depending upon the output of the logical AND. 18. The IC of claim 17 further comprising: a first register for storing the third bit; a second register coupled to the fourth multiplexer; a third register coupled to the output of the logical AND, an output of the third register controlling a third plurality of multiplexers; a first multiplexer of the third plurality of multiplexers coupled to the first register; and a second multiplexer of the third plurality of multiplexers coupled to the second register. 19. The IC of claim 17 wherein a carry look ahead circuit element of the plurality of carry look ahead circuit elements in the second group of the K groups comprises: a first m-bit carry look ahead adder adding together a zero carry-in, a m-bit subset of the sum set of bits plus at least two zero bits, and a second (m+1)-bit subset of the carry set of bits plus at least one zero bit; a second m-bit carry look ahead adder adding together a one carry-in, the m-bit subset of the sum set of bits plus at least two zero bits, and the (m+1)-bit subset of the carry set of bits plus at least one zero bit; and a multiplexer coupled to the first and second m-bit carry look ahead adders. 20. The IC of claim 12 wherein the IC is a programmable logic device (PLD).
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