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Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 UP-0807178 (2007-05-24)
등록번호 US-7855147 (2011-02-14)
발명자 / 주소
  • Dulkin, Alexander
  • Rairkar, Asit
  • Greer, Frank
  • Pradhan, Anshu A.
  • Rozbicki, Robert
출원인 / 주소
  • Novellus Systems, Inc.
대리인 / 주소
    Weaver Austin Villeneuve & Sampson LLP
인용정보 피인용 횟수 : 21  인용 특허 : 140

초록

Copper seed layers are formed on diffusion barrier layers (e.g., on Ta, and TaNx layers) without significant agglomeration of copper, with the use of an engineered barrier layer/seed layer interface. The engineered interface includes an adhesion layer, in which copper atoms are physically trapped an

대표청구항

What is claimed is: 1. A method of depositing a copper seed layer on a semiconductor substrate having a plurality of recessed features, the method comprising: (a) providing a semiconductor substrate having a barrier layer residing at least on the bottom portions and on the sidewalls of the recessed

이 특허에 인용된 특허 (140)

  1. Praburam Gopalraja ; Sergio Edelstein ; Avi Tepman ; Peijun Ding ; Debabrata Ghosh ; Nirmalya Maity, Alternate steps of IMP and sputtering process to improve sidewall coverage.
  2. Robert T. Rozbicki, Anti-agglomeration of copper seed layers in integrated circuit metalization.
  3. Lai Kwok Fai ; Hartsough Larry Dowd ; Nordquist Andrew L. ; Ashtiani Kaihan Abidi ; Levy Karl B. ; Biberger Maximilian A., Apparatus and method for controlling erosion profile in hollow cathode magnetron sputter source.
  4. Lai Kwok F. ; Nordquist Andrew L. ; Ashtiani Kaihan A. ; Hartsough Larry D. ; Levy Karl B., Apparatus and method for controlling plasma uniformity across a substrate.
  5. Fai Lai Kwok, Apparatus and method for improving target erosion in hollow cathode magnetron sputter source.
  6. Tobin, Jeffrey A.; Lu, Jean Qing; Mountsier, Thomas; Zhang, Hong Mei, Apparatus and method for physical vapor deposition using an open top hollow cathode magnetron.
  7. Klawuhn,Erich R.; Rozbicki,Robert; Dixit,Girish A., Apparatus and methods for deposition and/or etch selectivity.
  8. Wegmann Urs (Oberschan CHX) Rille Eduard (Dornbirn ATX), Apparatus for coating materials by cathode sputtering.
  9. Barnes Michael S. (Mahopac NY) Forster John C. (Poughkeepsie NY) Keller John H. (Newburgh NY), Apparatus for depositing material into high aspect ratio holes.
  10. Gates Stephen McConnell ; Neumayer Deborah Ann, Atomic layer deposition with nitrate containing precursors.
  11. Fiordalice, Robert W.; Pintchovski, Faivel, Barrier enhancement.
  12. Rozbicki,Robert; Danek,Michal, Barrier first method for single damascene trench applications.
  13. Lin, Jing-Cheng; Huang, Cheng-Lin; Shue, Winston; Liang, Mong-Song, Barrier free copper interconnect by multi-layer copper seed.
  14. Ding, Peijun; Chiang, Tony; Yao, Tse-Yong; Chin, Barry, Barrier layer for electroplating processes.
  15. Chen, Ling; Marcadal, Christophe, Barrier layer structure for copper metallization and method of forming the structure.
  16. Wei Wang ; Jianming Fu ; Praburam Gopalraja, Biased shield in a magnetron sputter reactor.
  17. Ruzic, David, Chemically-enhanced physical vapor deposition.
  18. Patton Evan E. ; Fetters Wayne, Clamshell apparatus for electrochemically treating semiconductor wafers.
  19. D'Couto, Gerard C.; Tkach, George; Woitge, Michael; Danek, Michal, Control of the deposition temperature to reduce the via and contact resistance of Ti and TiN deposited using ionized PVD techniques.
  20. Peijun Ding ; Tony Chiang ; Imran Hashim ; Bingxi Sun ; Barry Chin, Copper alloy seed layer for copper metallization.
  21. Dubin Valery ; Ting Chiu, Copper-aluminum metallization.
  22. Chiang, Tony; Yao, Gongda; Ding, Peijun; Chen, Fusen E.; Chin, Barry L.; Kohara, Gene Y.; Xu, Zheng; Zhang, Hong, Damage-free sculptured coating deposition.
  23. de Felipe, Tarek Suwwan; Danek, Michal; Klawuhn, Erich; Dulkin, Alexander, Deposition of conformal copper seed layers by control of barrier layer morphology.
  24. Dulkin, Alexander; Vijayendran, Anil; Yu, Tom; Juliano, Daniel R., Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer.
  25. Murthy Andiappan K. S. (Convent Station NJ) Bekker Alex Y. (Teaneck NJ) Patel Kundanbhai M. (Landing NJ), Deposition of thin films using supercritical fluids.
  26. Alfred Grill ; John Patrick Hummel ; Christopher Vincent Jahnes ; Vishnubhai Vitthalbhai Patel ; Katherine Lynn Saenger, Dual damascene processing for semiconductor chip interconnects.
  27. Bin Zhao ; Liming Tsau, Dual-damascene interconnect structures and methods of fabricating same.
  28. Contolini Robert J. ; Reid Jonathan ; Patton Evan ; Feng Jingbin ; Taatjes Steve ; Dukovic John Owen, Electric potential shaping method for electroplating.
  29. Reid Jonathan David ; Contolini Robert J. ; Dukovic John Owen, Electroplating anode including membrane partition system and method of preventing passivation of same.
  30. Reid Jonathan D. ; Taatjes Steven W. ; Contolini Robert J. ; Patton Evan E., Electroplating chamber with rotatable wafer holder and pre-wetting and rinsing capability.
  31. Somekh,Sasson R.; Schweitzer,Marc O.; Forster,John C.; Xu,Zheng; Mosely,Roderick C.; Chin,Barry L.; Grunes,Howard E., End point detection for sputtering and resputtering.
  32. Imai Nobuhiko (Sugito JPX) Sekiguchi Mamoru (Higashikawaguchi JPX) Kano Mitsuru (Kagurazaka JPX) Krug Thomas (Rodenbach DEX) Steiniger Gerhard (Ronneburg DEX) Meier Andreas (Pfullingen DEX), Evaporation method of forming transparent barrier film.
  33. Crockett Robert Nelson ; Kern Ronald Maynard ; McBride Gregory Edward, Extended remote copying system for reporting both active and idle conditions wherein the idle condition indicates no updates to the system for a predetermined time period.
  34. Kashiwada Kunio,JPX ; Kodama Takanori,JPX ; Taguchi Hiroyasu,JPX ; Hirano Satoshi,JPX, Fluorinated metal having a fluorinated layer and process for its production.
  35. Dalton, Jeremie; Powell, Ronald A.; Kailasam, Sridhar K.; Ramanathan, Sasangan, Forming metal-derived layers by simultaneous deposition and evaporation of metal.
  36. Powell, Ronald A.; Kailasam, Sridhar K.; Settles, E. Derryck; Lane, Larry R., High magnesium content copper magnesium alloys as diffusion barriers.
  37. Cuomo Jerome J. (Lake Lincolndale NY) Kaufman Harold R. (Fort Collins CO) Rossnagel Stephen M. (White Plains NY), Hollow cathode enhanced magnetron sputter device.
  38. Edwards ; III William H. (Port St. Lucie FL) Harris ; III John A. (West Palm Beach FL) Smith Edward S. (Lake Worth FL), Inhibiting coke formation by heat treating in nitrogen atmosphere.
  39. Claes H. Bjorkman ; Min Melissa Yu ; Hongquing Shan ; David W. Cheung ; Wai-Fan Yau ; Kuowei Liu ; Nasreen Gazala Chapra ; Gerald Yin ; Farhad K. Moghadam ; Judy H. Huang ; Dennis Yost ; B, Integrated low K dielectrics and etch stops.
  40. Gopalraja Praburam ; Fu Jianming ; Chen Fusen ; Dixit Girish ; Xu Zheng ; Athreya Sankaram ; Wang Wei D. ; Sinha Ashok K., Integrated process for copper via filling.
  41. Gopalraja Praburam ; Fu Jianming ; Chen Fusen ; Dixit Girish ; Xu Zheng ; Athreya Sankaram ; Wang Wei D. ; Sinha Ashok K., Integrated process for copper via filling using a magnetron and target producing highly energetic ions.
  42. Yang,Chih Chao; Hsu,Louis L.; Wong,Keith Kwong Hon; Dalton,Timothy Joseph; Radens,Carl; Clevenger,Larry, Interconnect structures and methods of making thereof.
  43. Yasar, Tugrul; Reynolds, Glyn; Cerio, Frank; Gittleman, Bruce; Grapperhaus, Michael; Robison, Rodney, Ionized PVD with sequential deposition and etching.
  44. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  45. Fu Jianming ; Gopalraja Praburam, Magnetron and target producing an extended plasma region in a sputter reactor.
  46. Ohmi Tadahiro (2-1-17-302 ; Komegafukuro Sendai-shi ; Miyagi-ken JPX) Miki Masahiro (23-14-521 ; Tezukayama 1-Chome Abeno-ku ; Osaka JPX) Kikuyama Hirohisa (7-13 ; 3-Cho ; Ayameike Kita Nara-shi ; Na, Metal material with film passivated by fluorination and apparatus composed of the metal material.
  47. Rostoker Norman (Irvine CA), Method and apparatus for accelerating charged particles.
  48. Hashim Imran ; Chiang Tony ; Chin Barry, Method and apparatus for forming improved metal interconnects.
  49. Hashim, Imran; Chiang, Tony; Chin, Barry, Method and apparatus for forming improved metal interconnects.
  50. Hashim, Imran; Chiang, Tony; Chin, Barry, Method and apparatus for forming improved metal interconnects.
  51. Hashim,Imran; Chiang,Tony; Chin,Barry, Method and apparatus for forming improved metal interconnects.
  52. Lantsman Alexander D., Method and apparatus for ionized sputtering.
  53. Reid Jonathan David ; Taatjes Steve, Method and apparatus for treating surface including virtual anode.
  54. Alessandra Satta BE; Karen Maex BE; Kai-Erik Elers FI; Ville Antero Saanila FI; Pekka Juha Soininen FI; Suvi P. Haukka FI, Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
  55. Rozbicki, Robert; Danek, Michal, Method for depositing a diffusion barrier for copper interconnect applications.
  56. Dubin Valery M., Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure.
  57. Lau, Gorley L., Method for forming a metallization structure in an integrated circuit.
  58. Joo Young-Chang ; Brown Dirk ; Chan Simon S., Method for forming conformal barrier layers.
  59. Wille,William C.; Edelstein,Daniel C.; Cote,William J.; Biolsi,Peter E.; Fritche,John; Upham,Allan W., Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material.
  60. You Lu ; Pramanick Shekhar ; Nogami Takeshi, Method for forming low dielectric passivation of copper interconnects.
  61. Iacoponi John A. ; Brown Dirk ; Nogami Takeshi, Method for forming semiconductor seed layers by inert gas sputter etching.
  62. Suntola Tuomo (Riihikallio 02610 Espoo 61 SF) Antson Jorma (Urheilutie 22 ; 01350 Vantaa 35 SF), Method for producing compound thin films.
  63. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX ; Bao Tien-I,TWX ; Jang Syun-Ming,TWX, Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby.
  64. Nihei Masayasu (Hitachi JPX) Onuki Jin (Hitachi JPX) Koubuchi Yasushi (Hitachi JPX) Miyazaki Kunio (Hitachi JPX) Itagaki Tatsuo (Tokyo JPX), Method of and apparatus for sputtering.
  65. Watkins James J. ; McCarthy Thomas J., Method of chemically depositing material onto a substrate.
  66. Imran Hashim ; Hong-Mei Zhang ; John C. Forster, Method of depositing a copper seed layer which promotes improved feature surface coverage.
  67. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  68. de Felipe, Tarek Suwwan; Danek, Michal; Klawuhn, Erich; Powell, Ronald A., Method of depositing a diffusion barrier for copper interconnection applications.
  69. Chiang,Tony; Yao,Gongda; Ding,Peijun; Chen,Fusen E.; Chin,Barry L.; Kohara,Gene Y.; Xu,Zheng; Zhang,Hong, Method of depositing a metal seed layer on semiconductor substrates.
  70. Ding,Peijun; Xu,Zheng; Zhang,Hong; Tang,Xianmin; Gopalraja,Praburam; Rengarajan,Suraj; Forster,John C.; Fu,Jianming; Chiang,Tony; Yao,Gongda; Chen,Fusen E.; Chin,Barry L.; Kohara,Gene Y., Method of depositing a tantalum nitride/tantalum diffusion barrier layer system.
  71. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing copper seed on semiconductor substrates.
  72. Patton Evan E. ; Fetters Wayne, Method of depositing metal layer.
  73. Pan Ju-Don T. (Austin TX), Method of deposition of metal into cavities on a substrate.
  74. Reid Jonathan D. ; Contolini Robert J. ; Opocensky Edward C. ; Patton Evan E. ; Broadbent Eliot K., Method of electroplating semicoductor wafer using variable currents and mass transfer to obtain uniform plated layer.
  75. Reid Jonathan D. ; Contolini Robert J. ; Opocensky Edward C. ; Patton Evan E. ; Broadbent Eliot K., Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer.
  76. Reid Jonathan D. ; Contolini Robert J. ; Opocensky Edward C. ; Patton Evan E. ; Broadbent Eliot K., Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer.
  77. Jing-Cheng Lin TW; Shau-Lin Shue TW; Chen-Hua Yu TW, Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process.
  78. Paul Rich GB, Method of forming a barrier layer.
  79. Geffken Robert M. ; Luce Stephen E., Method of forming a self-aligned copper diffusion barrier in vias.
  80. Woo, Christy Mei-Chu; Pangrle, Suzette K.; Wang, Connie Pin-Chin, Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer.
  81. Kim, Dong Joon, Method of forming multi layer conductive line in semiconductor device.
  82. Kenney Donald McAlpine, Method of forming stacked devices.
  83. Colgan Evan G. (Wappingers Falls NY) Fryer Peter M. (Mamaroneck NY), Method of making Alpha-Ta thin films.
  84. Schmidbauer Sven,DEX ; Ruf Alexander,DEX ; Schnabel Florian ; Hoinkis Mark ; Weber Stefan, Method of making a microelectronic structure.
  85. Nakasaki Yasushi (Yokohama JPX), Method of manufacturing a semiconductor device with a copper wiring layer.
  86. Huang Yimin,TWX ; Yew Tri-Rung,TWX ; Lur Water,TWX, Method of manufacturing copper interconnect.
  87. Chiang, Tony; Yao, Gongda; Ding, Peijun; Chen, Fusen E.; Chin, Barry L.; Kohara, Gene Y.; Xu, Zheng; Zhang, Hong, Method of preventing diffusion of copper through a tantalum-comprising barrier layer.
  88. Ling Chen ; Seshadri Ganguli ; Wei Cao ; Christophe Marcadal, Method of using a barrier sputter reactor to remove an underlying barrier layer.
  89. Chung-Shi Liu TW; Chen-Hua Yu TW, Method to improve copper process integration.
  90. Chen, Fusen; Chen, Ling; Glenn, Walter Benjamin; Gopalraja, Praburam; Fu, Jianming, Methods and apparatus for forming barrier layers in high aspect ratio vias.
  91. Angelo Darryl ; Sundarrajan Arvind ; Ding Peijun ; Tsung James H. ; Hong Ilyoung R. ; Chin Barry, Methods and apparatus for ionized metal plasma copper deposition with enhanced in-film particle performance.
  92. Tagami, Masayoshi; Hayashi, Yoshihiro, Multi-layered wiring layer and method of fabricating the same.
  93. Chiang, Tony P.; Cong, Yu D.; Ding, Peijun; Fu, Jianming; Tang, Howard H.; Tolia, Anish, Multi-step process for depositing copper seed layer in a via.
  94. Liu Joanna ; Xu Zheng, Multiple step ionized metal plasma deposition process for conformal step coverage.
  95. Rozbicki, Robert; van Schravendijk, Bart; Mountsier, Tom; Wu, Wen, Multistep method of depositing metal seed layers.
  96. Lai, Kwok F., Null-field magnetron apparatus with essentially flat target.
  97. Gerard Chris D'Couto ; George Tkach ; Jeff Dewayne Lyons ; Max Biberger ; Kwok Fai Lai ; Jean Lu ; Kaihan Ashtiani, PVD deposition of titanium and titanium nitride layers in the same chamber without use of a collimator or a shutter.
  98. Rumer,Michael; Griswold,Jack; Dorsh,Tom; Ng,Michael Kwok Leung; Reedy,David E.; Healey,Paul D.; Danek,Michal; Rosenberg,Reed W., PVD deposition process for enhanced properties of metal films.
  99. Lanford William A. ; Wang Wei ; Ding Peijun, Passivated copper conductive layers for microelectronic applications and methods of manufacturing same.
  100. Rozbicki, Robert T.; Powell, Ronald Allan; Klawuhn, Erich; Danek, Michal; Levy, Karl B.; Reid, Jonathan David; Khosla, Mukul; Broadbent, Eliot K., Passivation of copper in dual damascene metalization.
  101. Helmer John C. (260 S. Balsamina Way Palo Alto CA 94028) Lai Kwok F. (959 Van Auken Cir. Palo Alto CA 94303) Anderson Robert L. (3169 Emerson Palo Alto CA 94306), Physical vapor deposition employing ion extraction from a plasma.
  102. Matsuo Seitaro (Isehara JPX) Ono Toshiro (Isehara JPX), Plasma deposition method and apparatus.
  103. Ting Chiu ; Dubin Valery, Plated copper interconnect structure.
  104. Cyprian Emeka Uzoh, Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies.
  105. Stevens E. Henry ; Berner Robert W., Process architecture and manufacturing tool sets employing hard mask patterning for use in the manufacture of one or more metallization levels on a workpiece.
  106. Gordon Roy G. (Cambridge MA) Fix Renaud (Somerville MA) Hoffman David (Concord MA), Process for chemical vapor deposition of transition metal nitrides.
  107. Chen, Ling; Ganguli, Seshadri; Cao, Wei; Marcadal, Christophe, Process for removing an underlying layer and depositing a barrier layer in one reactor.
  108. Chao Tien S. (Hsinchu TWX) Chu Chih-Hsun (Hsinchu TWX), Process for suppressing boron penetration in BF2+-implanted P+-poly-Si gate us.
  109. Lanford William A. (Malden Bridge NY) Ding Peijun (Albany NY), Process of making oxidation resistant high conductivity copper layers.
  110. Sneh Ofer, Radical-assisted sequential CVD.
  111. Subrahmanyan, Suchitra; Chen, Liang-Yuh; Mosely, Roderick Craig, Reactive preclean prior to metallization for sub-quarter micron application.
  112. Lu, Jiong-Ping; Lin, Ching-Te, Reliable interconnects with low via/contact resistance.
  113. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Robust post Cu-CMP IMD process.
  114. Lin,Keng Chu; Cheng,Shwang Ming; Yeh,Ming Ling; Bao,Tien I, Sealing pores of low-k dielectrics using CH.
  115. Chung, Dean S.; Horak, David V.; Walton, Erick G., Selective deposition of a conductive material.
  116. Juliano, Daniel R., Selective resputtering of metal seed layers.
  117. Liao Kuan-Yang,TWX, Self-aligned metal nitride for copper passivation.
  118. Dubin Valery, Self-encapsulated copper metallization.
  119. Tanaka Masayuki,JPX ; Saida Shigehiko,JPX ; Tsunashima Yoshitaka,JPX, Semiconductor device and method of manufacturing the same.
  120. Xu Zheng ; Forster John ; Yao Tse-Yong, Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches.
  121. Venkatraman Ramnath ; Mendonca John ; Hamilton Gregory N. ; Wetzel Jeffrey T. ; Poon Tze W. ; Garcia Sam S., Semiconductor device with a copper barrier layer and formation thereof.
  122. Miyachi Kenji (Yokohama) Fukuda Nobuhiro (Yokohama) Ashida Yoshinori (Yokohama) Koyama Masato (Kamakura JPX), Semiconductor film and process for its production.
  123. Kailasam, Sridhar K.; Powell, Ronald A.; Settles, E. Derryck, Sputter apparatus for producing multi-component metal alloy films and method for making the same.
  124. Hurwitt Steven D. (Park Ridge NJ) Wagner Israel (Monsey NY) Hieronymi Robert (Rock Cavern NY) Van Nutt Charles (Monroe NY) Edwards Richard C. (Ringwood NJ) Messina Donald A. (Valley Cottage NY), Sputter coating process control method and apparatus.
  125. Chiang Tony ; Ding Peijun ; Chin Barry ; Hashim Imran ; Sun Bingxi, Sputter deposition and annealing of copper alloy metallization.
  126. Ding,Peijun; Zhang,Fuhong; Yang,Hsien Lung; Miller,Michael A.; Fu,Jianming; Yu,Jick M.; Xu,Zheng; Chen,Fusen, Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement.
  127. Morimoto, Naoki; Kondo, Tomoyasu; Nagashima, Hideto, Sputtering apparatus and film manufacturing method.
  128. Kobayashi Masahiko,JPX ; Takahashi Nobuyuki,JPX, Sputtering device and sputtering method.
  129. Yamazaki Shunpei (Tokyo JPX), Sputtering device for manufacturing superconducting oxide material and method therefor.
  130. Van Buskirk Peter C. ; Russell Michael W. ; Vestyck Daniel J. ; Summerfelt Scott R. ; Moise Theodore S., Sputtering process for the conformal deposition of a metallization or insulating layer.
  131. Praburam Gopalraja ; Jianming Fu, Sputtering target having an annular vault.
  132. Yu Chen-Hua Douglas (Hsin-Chu TWX), Step coverage enhancement process for sub half micron contact/via.
  133. Colgan Evan G. (Wappingers Falls NY) Fryer Peter M. (Mamaroneck NY), Structure and method of making Alpha-Ta in thin films.
  134. Savas, Stephen E.; Zajac, John; Kushner, Mark J.; Kinder, Ronald L., Systems and methods for enhancing plasma processing of a semiconductor substrate.
  135. Hirukawa Yohichi (Tokyo JPX) Nozaki Toshiyuki (Tokyo JPX) Hosokawa Naokichi (Tokyo JPX), Target assembly capable of attaining a high step coverage ratio in a magnetron-type sputtering device.
  136. Toyokura Nobuo (Kawasaki JPX) Ohnishi Toyokazu (Isehara JPX) Yokoyama Naoki (Atsugi JPX), Thin film resistor for an integrated circuit semiconductor device.
  137. D'Couto, Gerard C.; Tkach, George; Danek, Michal, Use of RF biased ESC to influence the film properties of Ti and TiN.
  138. Praburam Gopalraja ; Jianming Fu ; Fusen Chen ; Girish Dixit ; Zheng Xu ; Wei Wang ; Ashok K. Sinha, Vault shaped target and magnetron operable in two sputtering modes.
  139. Praburam Gopalraja ; Jianming Fu ; Wei Wang, Vault-shaped target and magnetron having both distributed and localized magnets.
  140. Lee Chang-Jae (Choongchungbook-Do KRX), Wiring structure for semiconductor device and fabrication method therefor.

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  3. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
  4. Shaviv, Roey; Gopinath, Sanjay; Holverson, Peter; Pradhan, Anshu A., Conformal films on semiconductor substrates.
  5. Dyer, Thomas W.; Edelstein, Daniel C.; Ko, Tze-man; Simon, Andrew H.; Tseng, Wei-tsu, Doping of copper wiring structures in back end of line processing.
  6. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
  7. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
  8. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
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  10. Kunihiro, Takafumi, Memory programming methods and memory systems.
  11. Kunihiro, Takafumi, Memory programming methods and memory systems.
  12. Rozbicki, Robert T.; Danek, Michal; Klawuhn, Erich R., Method of depositing a diffusion barrier for copper interconnect applications.
  13. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  14. Rozbicki, Robert; Danek, Michal; Klawuhn, Erich, Method of depositing a diffusion barrier for copper interconnect applications.
  15. Yu, Wen; Robie, Stephen B.; Romero, Jeremias D., Method of depositing copper using physical vapor deposition.
  16. Rozbicki, Robert, Methods and apparatus for resputtering process that improves barrier coverage.
  17. Moon, Hyo-Jeong; Noh, Woo-Choel; Jang, Woo-Jin; Kim, Hun; Shin, Hong-Jae, Methods of manufacturing semiconductor devices.
  18. Spooner, Terry A.; Wang, Wei; Yang, Chih-chao, Multiple pre-clean processes for interconnect fabrication.
  19. Rozbicki, Robert; van Schravendijk, Bart; Mountsier, Thomas; Wu, Wen, Multistep method of depositing metal seed layers.
  20. Naik, Mehul; Ma, Paul F.; Nemani, Srinivas D., Protective via cap for improved interconnect performance.
  21. Haneda, Masaki; Shimizu, Noriyoshi; Ohtsuka, Nobuyuki; Nakao, Yoshiyuki; Sunayama, Michie; Tabira, Takahiro, Semiconductor device with reduced increase in copper film resistance.

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AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트