초록 ▼

A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface

A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

대표청구항 ▼

Having thus described the invention, what is claimed as new and desirable to be secured by Letters Patent is as follows: 1. A silicon based package (SBP) comprising: an ultra thin silicon wafer (UTSW) composed of silicon and having a first surface of silicon and a reverse surface; metal capture str

Having thus described the invention, what is claimed as new and desirable to be secured by Letters Patent is as follows: 1. A silicon based package (SBP) comprising: an ultra thin silicon wafer (UTSW) composed of silicon and having a first surface of silicon and a reverse surface; metal capture structures each having a first surface formed directly on the first surface of silicon of the UTSW and an exposed surface; an interconnection structure formed over the first surface of the UTSW and the exposed surface of the metal capture structures; vertical sidewall through via (VSTV) holes formed in the SBP with hole sidewalls that extend from the reverse surface through the UTSW to the first surface of the metal capture structures; a layer of dielectric material covering at least the sidewalls of the VSTV holes leaving at least a portion of the first surface of the metal capture structures exposed; and ball limiting metallurgy (BLM) comprising a layer of metal covering the exposed portion of the metal capture structures and the layer of dielectric material on the sidewalls of the VSTV holes to form metal lined sidewalls in the VSTV holes which metal lined sidewalls extend through the UTSW into contact with the layer of metal covering the exposed portion of the metal capture structures to form a metal lined recessed via pad structure in the UTSW extending to the metal capture structures to allow solder ball contact with the metal lined sidewalls and the layer of metal covering the exposed portion of the metal capture structures. 2. The silicon based package of claim 1 further including a solder ball formed in the metal lined recessed via pad structure in contact with the metal capture structures. 3. A silicon based package (SBP) comprising: an ultra thin silicon wafer (UTSW) composed of silicon having a first surface of silicon and a reverse surface and a thickness of about 50-75 μm; metal capture structures each having a first surface formed directly on the first surface of silicon of the UTSW and an exposed surface; an interconnection structure formed over the first surface of the UTSW and the exposed surface of the metal capture structures; vertical sidewall through via (VSTV) holes formed in the SBP with hole sidewalls that extend from the reverse surface through the UTSW to the first surface of the metal capture structures with the wall angle of the VSTV holes tapered from the reverse surface to the first surface; a layer of dielectric material covering at least the sidewalls of the VSTV holes leaving at least a portion of the first surface of the metal capture structures exposed; and ball limiting metallurgy (BLM) comprising a layer of metal covering the exposed portion of the metal capture structures and the layer of dielectric material on the sidewalls of the VSTV holes to form metal lined sidewalls in the VSTV holes which metal lined sidewalls extend through the UTSW into contact with the layer of metal covering the exposed portion of metal capture structures to form a metal lined_recessed via pad structure in the UTSW extending to the metal capture structures to allow solder ball contact with the metal lined sidewalls and the layer of metal covering the exposed portion of the metal capture structures. 4. The silicon based package of claim 3 further including a solder ball formed in the metal lined recessed via pad structure in contact with the metal capture structures. 5. The silicon based package of claim 3 wherein the wall angle of the VSTV holes formed in the SBP are taped at about 45 degrees. 6. The silicon based package of claim 5 wherein the wall angle of the USTV holes have an opening at the reverse surface of 300 μm and an opening at the first surface of 150 μm. 7. The silicon based package of claim 3 wherein the wall angle of the VSTV holes formed in the SBP are substantially vertical.