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Chip structure with bumps and testing pads

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/43
출원번호 UP-0127794 (2008-05-27)
등록번호 US-7855461 (2011-02-14)
발명자 / 주소
  • Kuo, Nick
  • Chou, Chiu-Ming
  • Chou, Chien-Kang
  • Lin, Chu-Fu
출원인 / 주소
  • Megica Corporation
대리인 / 주소
    McDermott Will & Emery LLP
인용정보 피인용 횟수 : 7  인용 특허 : 158

초록

A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substra

대표청구항

What is claimed is: 1. A chip comprising: a silicon substrate; multiple MOS devices in or on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first circuit layer

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  7. Chen, Yu-Feng; Tsai, Yu-Ling; Pu, Han-Ping; Kuo, Hung-Jui; Huang, Yu Yi, Wafer level chip scale package with reduced stress on solder balls.
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