초록 ▼

A method is provided for making a crystalline silicon solar cell on a low purity substrate by depositing p+-p-n+, or n+-n-p+ layers of amorphous silicon, depending on the type of wafer, on a crystalline silicon substrate, such as an upgraded metallurgical grade silicon substrate, with substrate vias

A method is provided for making a crystalline silicon solar cell on a low purity substrate by depositing p+-p-n+, or n+-n-p+ layers of amorphous silicon, depending on the type of wafer, on a crystalline silicon substrate, such as an upgraded metallurgical grade silicon substrate, with substrate vias of varying diameters formed thereon, annealing the stack of amorphous silicon layers to cause solid phase epitaxial crystallization, and metallizing the substrate assembly using standard metallization techniques. One embodiment of the present invention provides depositing a passivation layer onto the third deposited silicon layer subsequent to the crystallization. Another embodiment provides depositing a passivation layer on the back side of the substrate subsequent to crystallization and punching selected regions at the substrate vias prior to back metallization.

대표청구항 ▼

The invention claimed is: 1. A method for forming a crystalline silicon solar cell comprising: forming vias of two different diameters through a crystalline silicon substrate from a first surface to a second surface; depositing a first silicon layer on the first surface of the crystalline silicon s

The invention claimed is: 1. A method for forming a crystalline silicon solar cell comprising: forming vias of two different diameters through a crystalline silicon substrate from a first surface to a second surface; depositing a first silicon layer on the first surface of the crystalline silicon substrate and on surfaces within the vias, wherein the first silicon layer fills vias of lesser diameter; depositing a second silicon layer over the first silicon layer, wherein the second silicon layer fills vias of greater diameter; depositing a third silicon layer over the second silicon layer; and depositing a metallization layer on the second surface of the crystalline silicon substrate. 2. The method of claim 1, further comprising depositing a passivation layer on the third silicon layer prior to depositing the metallization layer on the second surface and forming metal contacts on selected areas of the third silicon layer. 3. The method of claim 2, wherein the passivation layer is formed from a compound selected from the group consisting of silicon nitride and silicon oxide. 4. The method of claim 1, wherein the crystalline silicon substrate is a p-type silicon substrate, the first silicon layer is a p+-type amorphous silicon layer, the second silicon layer is a p-type amorphous silicon layer and the third silicon layer is an n+-type amorphous silicon layer. 5. The method of claim 1, further comprising annealing the crystalline silicon substrate, prior to depositing the metallization layer, at a temperature sufficient to cause crystallization of the first, second and third silicon layers and to electrically activate dopants in the layers. 6. The method of claim 1, wherein the vias are formed by laser ablation. 7. The method of claim 1, wherein the vias of two different diameters comprise a first via having a diameter of about 4 microns to about 15 microns and a second via having a diameter of about 40 microns to about 60 microns. 8. The method of claim 1, wherein the second silicon layer is 20 to 30 microns thick. 9. The method of claim 1, further comprising removing saw damage from the substrate surfaces and texture etching the crystalline silicon substrate prior to forming the vias. 10. The method of claim 1, wherein the crystalline silicon substrate comprises an upgraded metallurgical grade crystalline silicon substrate having a concentration of boron or phosphorus of about 1×1016 atoms/cm3 to about 1×1019 atoms/cm3. 11. A method for forming a crystalline silicon solar cell comprising: forming vias of two different diameters through a crystalline silicon substrate from a first surface to a second surface; depositing a first silicon layer on the first surface of the crystalline silicon substrate and on surfaces within the vias, wherein the first silicon layer fills vias of lesser diameter; depositing a second silicon layer on the first silicon layer; depositing a third silicon layer on the second silicon layer, wherein the third silicon layer fills vias of greater diameter; depositing a passivation layer on the second surface of the substrate; patterning the passivation layer to expose portions of the first silicon layer and the third silicon layer; and depositing a conductive layer over the patterned passivation layer so that the conductive layer makes contact with the exposed regions of the first silicon layer in the vias of lesser diameter and the third silicon layer in the vias of greater diameter. 12. The method of claim 11, further comprising annealing the substrate, prior to depositing the passivation layer and depositing the conductive layer, at a temperature sufficient to cause crystallization of the first, second and third silicon layers and to electrically activate dopants in the layers. 13. The method of claim 12, further comprising depositing a second passivation layer on the third silicon layer after annealing. 14. The method of claim 12, further comprising depositing a second passivation layer on the third silicon layer after annealing, wherein the second passivation layer comprises two or more layers. 15. The method of claim 12, further comprising depositing a second passivation layer on the third silicon layer after annealing, wherein the second passivation layer comprises two or more layers and wherein either of the layers of the second passivation layer is formed from a compound selected from the group consisting of silicon nitride and silicon oxide. 16. The method of claim 11, wherein the crystalline silicon substrate is a p-type silicon substrate, the first silicon layer is a p+-type amorphous silicon layer, the second silicon layer is a p-type amorphous silicon layer and the third silicon layer is an n+-type amorphous silicon layer. 17. The method of claim 11, wherein the crystalline silicon substrate comprises an upgraded metallurgical grade crystalline silicon substrate having a concentration of boron or phosphorus of about 1×1016 atoms/cm3 to about 1×1019 atoms/cm3. 18. A method for forming a crystalline silicon solar cell comprising: forming vias of two different diameters through a crystalline silicon substrate from a first surface to a second surface; depositing a first silicon layer over the first surface of the crystalline silicon substrate and on surfaces within the vias, wherein the first silicon layer fills vias of lesser diameter; depositing a second silicon layer over the first silicon layer; depositing a third silicon layer over the second silicon layer, wherein vias of greater diameter remain open after deposition of the first, second and third silicon layers; depositing a passivation layer over the second surface of the crystalline silicon substrate; patterning the passivation layer to expose regions of the first silicon layer and the third silicon layer; and depositing a conductive layer over the patterned passivation layer so that the conductive layer contacts the exposed regions of the first silicon layer in the vias of lesser diameter and the third silicon layer in the vias of greater diameter. 19. The method of claim 18, further comprising depositing a second passivation layer on the third silicon layer prior to deposition of the passivation layer over the second surface. 20. The method of claim 19, wherein the second passivation layer comprises two or more layers. 21. The method of claim 19, wherein the second passivation layer comprises two or more layers, and wherein either of the layers of the second passivation layer is formed from a compound selected from the group consisting of silicon nitride and silicon oxide. 22. The method of claim 18, wherein the first layer is a p+-type amorphous silicon layer, the second layer is a p-type amorphous silicon layer, and the third layer is a n+-type amorphous silicon layer. 23. The method of claim 18, further comprising annealing the substrate, prior to depositing the passivation layer and depositing the conductive layer, at a temperature sufficiently low to cause solid phase epitaxial crystallization of the first, second, and third silicon layers and to electrically activate dopants in the layers. 24. The method of claim 18, wherein the crystalline silicon substrate comprises an upgraded metallurgical grade crystalline silicon substrate having a concentration of boron or phosphorus of about 1×1016 atoms/cm3 to about 1×1019 atoms/cm3.