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An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation o

An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.

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What is claimed is: 1. A method of forming a semiconductor structure comprising:forming a stack, from bottom to top, of a gate dielectric layer, a gate conductor layer, a dielectric oxide layer, and a semiconductor layer on a semiconductor substrate;forming crystallographic facets joined by a ridge

What is claimed is: 1. A method of forming a semiconductor structure comprising:forming a stack, from bottom to top, of a gate dielectric layer, a gate conductor layer, a dielectric oxide layer, and a semiconductor layer on a semiconductor substrate;forming crystallographic facets joined by a ridge in said semiconductor layer by an anisotropic wet etch;forming a masking material layer on said crystallographic facets;forming implantation-damaged masking material portions by implanting Ge, B, Ga, In, As, P, Sb, or inert atoms into said masking material layer, whereby a portion of said masking material layer is not implanted by said Ge, B, Ga, In, As, P, Sb, or inert atoms to form an undamaged masking material portion;removing said implantation-damaged masking material portions selective to said undamaged masking material portion; andetching said semiconductor layer and said dielectric oxide layer employing said undamaged masking material portion as an etch mask.