초록 ▼

A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blo

A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.

대표청구항 ▼

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows: 1. A method of reducing power consumption in a microprocessor having at least one storage structure, said method comprising:dynamically measuring an activity of said at least one storage s

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows: 1. A method of reducing power consumption in a microprocessor having at least one storage structure, said method comprising:dynamically measuring an activity of said at least one storage structure; andcontrolling a size of said at least one storage structure based on said measurement,wherein no more than approximately 3% additional circuitry is added to said at least one storage structure for said reducing power consumption, said additional circuitry being measured in terms of a number of additional transistors added to said at least one storage structure to achieve said activity measuring and said size controlling, said reducing power consumption being relative to a power consumption if said at least one storage structure operates with no size reduction.