초록 ▼

An automatic hold time fixing circuit unit includes a first switch having first and second ends connected to data input and output ports. An input end of a memory element is connected to the second end of the first switch. A second switch includes a first end connected to an output end of the memory

An automatic hold time fixing circuit unit includes a first switch having first and second ends connected to data input and output ports. An input end of a memory element is connected to the second end of the first switch. A second switch includes a first end connected to an output end of the memory element and a second end connected to the data output port. A control circuit includes first and second output terminals and first and second input terminals. The first and second output terminals are connected to control ends of the first and second switches. The first and second input terminals allow input of two clocks to the control circuit for controlling connection or disconnection of the first and second switches. The data stored in the memory element can be utilized to fix a hold time of the data, so that correct data can be obtained at the data output port.

대표청구항 ▼

What is claimed is: 1. An automatic hold time fixing circuit unit comprising:a first switch including first and second ends electrically connected to a data input port and a data output port, respectively, with the first switch further including a control end controlling connection or disconnection

What is claimed is: 1. An automatic hold time fixing circuit unit comprising:a first switch including first and second ends electrically connected to a data input port and a data output port, respectively, with the first switch further including a control end controlling connection or disconnection of the first and second ends of the first switch;a memory element including an input end and an output end, with the input end of the memory element electrically connected to the second end of the first switch;a second switch including a first end electrically connected to the output end of the memory element and a second end electrically connected to the data output port, with the second switch further including a control end controlling connection or disconnection of the first and second ends of the second switch; anda control circuit including a first output terminal, a second output terminal, a first input terminal, and a second input terminal, with the first and second output terminals electrically connected to the control ends of the first and second switches, respectively, with the first and second input terminals allowing input of two clocks to the control circuit for controlling connection or disconnection of the first and second switches,wherein the control circuit includes an AND gate and first and second inverters, with the AND gate including a first input port forming the first input terminal, with the AND gate further including a second input port electrically connected to an output end of the first inverter, with the AND gate further including an output port forming the second output terminal, with the first inverter including an input end forming the second input terminal, with the second inverter including an input end electrically connected to the output port of the AND gate, and with the second inverter further including an output end forming the first output terminal.