초록 ▼

In one disclosed embodiment, an input bit stream is supplied to a trellis code block. For example, the trellis code block can perform convolutional coding using a rate 6/7 code. The output of the trellis code block is then modulated using, for example, trellis coded quadrature amplitude modulation w

In one disclosed embodiment, an input bit stream is supplied to a trellis code block. For example, the trellis code block can perform convolutional coding using a rate 6/7 code. The output of the trellis code block is then modulated using, for example, trellis coded quadrature amplitude modulation with 128 signal points or modulation symbols. The sequence of modulation symbols thus generated can be diversity encoded. The diversity encoding can be either a space time encoding, for example, or a space frequency encoding. The sequence of modulation symbols, or the sequence of diversity encoded modulation symbols, is fed to two or more orthogonal Walsh covers. For example, replicas of the modulation symbol sequences can be provided to increase diversity, or demultiplexing the modulation symbol sequences can be used to increase data transmission rate or “throughput.” The outputs of the Walsh covers are fed as separate inputs into a communication channel.

대표청구항 ▼

The invention claimed is: 1. A method comprising performing the steps in the order presented:supplying an input bit stream to a channel coding block;modulating an output of the channel coding block to provide a modulation symbol sequence and frequency coding the modulation symbol sequence;feeding a

The invention claimed is: 1. A method comprising performing the steps in the order presented:supplying an input bit stream to a channel coding block;modulating an output of the channel coding block to provide a modulation symbol sequence and frequency coding the modulation symbol sequence;feeding a replica of the entire frequency coded modulation symbol sequence to each of a plurality of orthogonal sequence covers, wherein each of the plurality of orthogonal sequence covers outputs one of a plurality of spread sequences of output chips;performing inverse Fast Fourier Transform (FFT) and cyclic prefix processing on the plurality of spread sequences of output chips to yield a plurality of outputs; andtransmitting the plurality of outputs over a multiple-input multiple-output channel.