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Barrier layer configurations and methods for processing microelectronic topographies having barrier layers

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0719167 (2010-03-08)
등록번호 US7897507 (2011-02-15)
발명자 / 주소
  • Ivanov, Igor C.
출원인 / 주소
  • Lam Research Corporation
대리인 / 주소
    Daffer McDaniel, LLP
인용정보 피인용 횟수 : 3  인용 특허 : 33

초록

A microelectronic topography includes a dielectric layer (DL) with a surface higher than an adjacent bulk metal feature (BMF) and further includes a barrier layer (BL) upon the BMF and extending higher than the DL. Another microelectronic topography includes a BL with a metal-oxide layer having a me

대표청구항

What is claimed is: 1. A method for processing a microelectronic topography, comprising:forming a diffusion barrier layer upon and in contact with a bulk metal feature such that portions of a first dielectric layer arranged adjacent to the bulk metal feature are exposed;selectively depositing a seco

이 특허에 인용된 특허 (33)

  1. Ivanov, Igor; Zhang, Jonathan Weiguo; Kolics, Artur, Apparatus and method for electroless deposition of materials on semiconductor substrates.
  2. Fukuzumi, Yoshiaki; Kohyama, Yusuke, Capacitor having a structure capable of restraining deterioration of dielectric film, semiconductor device having the capacitor and method of manufacturing the same.
  3. Kirlin Peter S. ; Van Buskirk Peter C., Chemical mechanical polishing of FeRAM capacitors.
  4. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  5. Dhote Anil M. ; Ramesh Ramamoorthy, Electrode structure for ferroelectric capacitor integrated on silicon.
  6. Chebiam, Ramanan V.; Dubin, Valery M., Electroless plating bath composition and method of using.
  7. Inoue, Hiroaki; Nakamura, Kenji; Matsumoto, Moriji, Electroless plating liquid and semiconductor device.
  8. Inoue, Hiroaki; Nakamura, Kenji; Matsumoto, Moriji, Electroless plating liquid and semiconductor device.
  9. Stevens, Joseph J.; Lubomirsky, Dmitry; Pancham, Ian; Olgado, Donald J.; Grunes, Howard E.; Mok, Yeuk-Fai Edwin; Dixit, Girish, Electroless plating system.
  10. Graff, Gordon L.; Gross, Mark E.; Affinito, John D.; Shi, Ming-Kun; Hall, Michael G.; Mast, Eric S.; Walty, Robert; Rutherford, Nicole; Burrows, Paul E.; Martin, Peter M., Environmental barrier material for organic light emitting device and method of making.
  11. Pin-Chin C. Wang ; Sergey Lopatin, Formation of alloy material using alternating depositions of alloy doping element and bulk material.
  12. Johnston,Steven W.; Dubin,Valery M.; McSwiney,Michael L.; Moon,Peter, Forming a copper diffusion barrier.
  13. Lopatin, Sergey; Wang, Fei; Schonauer, Diana; Avanzino, Steven C., Interconnect structure formed in porous dielectric material with minimized degradation and electromigration.
  14. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Interconnect structures and a method of electroless introduction of interconnect structures.
  15. Segawa, Yuji; Yoshio, Akira; Suzuki, Masatoshi; Watanabe, Katsumi; Sato, Shuzo, Method of electroless plating and electroless plating apparatus.
  16. Chan Lap ; Li Sam Fong Yau,SGX ; Ng Hou Tee,SGX, Method to encapsulate copper plug for interconnect metallization.
  17. Ivanov, Igor C.; Zhang, Weiguo, Methods and system for processing a microelectronic topography.
  18. Ivanov, Igor C.; Zhang, Welguo, Microelectronic fabrication system components and method for processing a wafer using such components.
  19. Danek Michal ; Levy Karl B., Multilayer diffusion barriers.
  20. Ramanathan, Sivakami; Padhi, Deenesh; Gandikota, Srinivas; Dixit, Girish A., Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application.
  21. Ting Chiu H. ; Holtkamp William H. ; Ko Wen C. ; Lowery Kenneth J. ; Cho Peter, Process chamber and method for depositing and/or removing material on a substrate.
  22. Kuroda,Osamu; Taniyama,Hiroki; Toshima,Takayuki, Processing apparatus and substrate processing method.
  23. van Schravendijk,Bart; Mountsier,Thomas W; Sanganeria,Mahesh K; Alers,Glenn B; Shaviv,Roey, Protection of Cu damascene interconnects by formation of a self-aligned buffer layer.
  24. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  25. Yang, Kai; Nogami, Takeshi; Brown, Dirk; Pramanick, Shekhar, Self-aligned semiconductor interconnect barrier and manufacturing method therefor.
  26. Sergey D. Lopatin ; Carl J. Galewski, Semiconductor catalytic layer and atomic layer deposition thereof.
  27. Asahina Michio,JPX ; Matsumoto Kazuki,JPX ; Suzuki Eiji,JPX, Semiconductor device and method of fabricating the same.
  28. Nogami, Takeshi; Komai, Naoki; Kito, Hideyuki; Taguchi, Mitsuru, Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof.
  29. Nakano, Hiroshi; Itabashi, Takeyuki; Akahoshi, Haruo, Semiconductor device having cobalt alloy film with boron.
  30. Lopatin Sergey D. ; Pramanick Shekhar ; Brown Dirk, Semiconductor metalization barrier.
  31. Nishimura Joichi,JPX ; Morita Akihiko,JPX ; Ohtani Masami,JPX, Substrate cleaning apparatus and method.
  32. Akira Fujisawa JP; Akihito Takano JP; Masayuki Sasaki JP, Thin film capacitance device and printed circuit board.
  33. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (3)

  1. Ivanov, Igor C., Barrier layer configurations and methods for processing microelectronic topographies having barrier layers.
  2. Ivanov, Igor C., Method for passivating hardware of a microelectronic topography processing chamber.
  3. Ivanov, Igor C., Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes.
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