초록 ▼

An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which

An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller. The control circuitry, when connected to the emulation controller, effects the providing and receiving of signals and the transferring of serial data between the emulation controller and the emulator continuously without interruption while the first state machine remains in one state.

대표청구항 ▼

What is claimed is: 1. An integrated circuit comprising;A. functional input leads;B. functional output leads;C. a TDI input lead;D. a TMS input lead;E. a TCK input lead;F. a TDO output lead;G. a TAP controller that includes a first state machine circuit, the TAP controller having inputs connected to

What is claimed is: 1. An integrated circuit comprising;A. functional input leads;B. functional output leads;C. a TDI input lead;D. a TMS input lead;E. a TCK input lead;F. a TDO output lead;G. a TAP controller that includes a first state machine circuit, the TAP controller having inputs connected to the TMS and TCK input leads and TAP control outputs;H. an instruction register having control inputs connected to the TAP control outputs, a data input connected to the TDI input lead, a data output coupled to the TDO output lead, and instruction control outputs;I. parallel scan registers each having control inputs connected to the instruction control outputs, a data input and a data output;J. input switch circuits, one for each parallel scan register, each input switch circuit having a functional input connected to one functional input lead, a serial input connected to the TDI input lead, a control input connected to the instruction control outputs, and an output connected to the data input of one parallel scan register;K. output switch circuits, one for each parallel scan register, each output switch circuit having a serial input connected to the data output of one parallel scan register, a functional output connected to one functional output lead, and a control input connected to the instruction control outputs; andL. serializer circuits, one for each parallel scan register, each serializer circuit having a serial input connected with the TDI input lead, a serial output coupled with the TDO output lead, a TAP control input connected with the TAP control outputs, an instruction control input connected with the instructions control outputs, and a control output connected with a control input of a parallel scan register.