초록 ▼

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizi

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

대표청구항 ▼

What is claimed is: 1. A semiconductor device comprising:a pixel section comprising a pixel TFT over a substrate;a driver circuit comprising an n-channel TFT and a p-channel TFT over the substrate;wherein each of the pixel TFT and the n-channel TFT comprises:a semiconductor layer comprising a channe

What is claimed is: 1. A semiconductor device comprising:a pixel section comprising a pixel TFT over a substrate;a driver circuit comprising an n-channel TFT and a p-channel TFT over the substrate;wherein each of the pixel TFT and the n-channel TFT comprises:a semiconductor layer comprising a channel forming region, a pair of LDD regions in contact with the channel forming region, and source and drain regions disposed on the outside of the pair of LDD regions;a gate insulating film provided over the semiconductor layer, wherein a thickness of the gate insulating film over the channel region is thicker than a thickness of the gate insulating film over each of the source and drain regions; anda gate electrode provided over the gate insulating film, and overlapping a portion of the pair of LDD regions, andwherein the p-channel TFT comprises:a semiconductor layer comprising a channel forming region, a pair of LDD regions in contact with the channel forming region, and source and drain regions disposed on the outside of the pair of LDD regions;a gate insulating film provided over the semiconductor layer, wherein a thickness of the gate insulating film over the channel region is thicker than a thickness of the gate insulating film over each of the source and drain regions;a gate electrode provided over the gate insulating film, and overlapping the pair of LDD regions, entirely.