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Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline. A record instruction including a record start address is sent to the extended pipeline. The extended pipeline thus begins recording the subsequent instruction

Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline. A record instruction including a record start address is sent to the extended pipeline. The extended pipeline thus begins recording the subsequent instruction sequence at the specified address until an end record instruction is encountered. The end record instruction is recorded as the last instruction in the sequence. The main pipeline may then call the instruction sequence by sending a run instruction including the start address for the desired sequence to the extended pipeline. This run instruction causes the extended pipeline to begin autonomously executing the recorded sequence until the end record instruction is encountered. This instruction causes the extended pipeline to cease autonomous execution and to return to executing instructions supplied by the main pipeline.

대표청구항 ▼

The invention claimed is: 1. A microprocessor architecture having decoupled fetch-execution cycles for at least two instruction pipelines, comprising:a main instruction pipeline operating at a first clock frequency; andan extended instruction pipeline,wherein the main instruction pipeline is configu

The invention claimed is: 1. A microprocessor architecture having decoupled fetch-execution cycles for at least two instruction pipelines, comprising:a main instruction pipeline operating at a first clock frequency; andan extended instruction pipeline,wherein the main instruction pipeline is configured to issue:a begin record instruction to the extended instruction pipeline, causing the extended instruction pipeline to begin recording a sequence of instructions issued by the main instruction pipeline; anda single instruction comprising a starting address of the sequence of recorded instructions to the extended instruction pipeline, causing the extended instruction pipeline to execute the sequence of recorded instructions;wherein the single instruction or the begin record instruction causes the extended instruction pipeline to switch to an autonomous mode of operation from a main instruction pipeline controlled mode of operation,wherein operating in the autonomous mode of operation comprises fetching and executing instructions from the sequence of recorded instructions independent from the main instruction pipeline, through a front end portion of the extended instruction pipeline, the front end portion of the extended instruction pipeline operating at a second clock frequency that is different from the first clock frequency, thereby decoupling the fetch-execution cycles of the main instruction pipeline from the extended instruction pipeline.