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Allocation of combined or separate data and control planes 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0186622 (2008-08-06)
등록번호 US7975250 (2011-06-22)
발명자 / 주소
  • Honary, Hooman
  • Chen, Inching
  • Tsui, Ernest T.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Cool Patent, P.C.
인용정보 피인용 횟수 : 0  인용 특허 : 30

초록

A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

대표청구항

What is claimed is: 1. An integrated circuit, comprising:a heterogeneous network of processing elements, at least one of the processing elements being capable of receiving a radio-frequency signal;first and second mesh interconnect networks coupled to the heterogeneous network of processing elements

이 특허에 인용된 특허 (30)

  1. Honary,Hooman; Chen,Inching; Tsui,Ernest T., Allocation of combined or separate data and control planes.
  2. Schmitz Nicholas A. (Cupertino CA), Apparatus and method for allocation of resoures in programmable logic devices.
  3. Fujii, Taro; Motomura, Masato; Furuta, Koichiro, Array type processor with state transition controller identifying switch configuration and processing element instruction address.
  4. Mattias 0stman SE; Lars-Goran Petersen SE, Combined header parameter table for ATM node.
  5. Shou Guoliang,JPX ; Zhou Changming,JPX ; Yamamoto Makoto,JPX ; Sawahashi Mamoru,JPX ; Adachi Fumiyuki,JPX ; Takatori Sunao,JPX, Communication method and system using different spreading codes.
  6. Tsai,Vicki W.; Honary,Hooman; Tsui,Ernest T., Constraints-directed compilation for heterogeneous reconfigurable architectures.
  7. Aldrich, Bradley C.; Kolagotla, Ravi, DSP unit for multi-level global accumulation.
  8. Sugeno Yukio,JPX ; Yoshida Takeshi,JPX, Data split parallel shifter and parallel adder/subtractor.
  9. Godfrey Gary M. ; Hartmann Alfred C., Data transfer network on a computer chip using a re-configurable path multiple ring topology.
  10. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  11. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  12. Heile Francis B. ; Fairbanks Brent A., Incremental compilation of electronic design for work group.
  13. Alidina Mazhar M. ; Simanapalli Sivanand, Mac processor with efficient Viterbi ACS operation and automatic traceback store.
  14. Leaver Andrew ; Heile Francis B., Mapping heterogeneous logic elements in a programmable logic device.
  15. Mirsky Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.
  16. Hwang, L. James; Sanchez, Reno L., Method and system for integrating cores in FPGA-based system-on-chip (SoC).
  17. Jain Gitu, Method for controlling power and slew in a programmable logic device.
  18. Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L. ; Fromm Eric C., Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers.
  19. Dent,Peter R., Multiple bit complex bit modulation.
  20. Freitag ; Jr. William W., Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions.
  21. Dietz, Russell S.; Koppenhaver, Andrew A.; Torgerson, James F., Processing protocol specific information in packets specified by a protocol description language.
  22. John Susantha Fernando ; Stefan Thurnhofer, Programmable accelerator for a programmable processor system.
  23. Furuta Koichiro,JPX ; Fujii Taro,JPX ; Motomura Masato,JPX, Programmable device with an array of programmable cells and interconnection network.
  24. Dietz, Russell S.; Maixner, Joseph R.; Koppenhaver, Andrew A., Re-using information from data transactions for maintaining statistics in network monitoring.
  25. Leyonhjelm, Scott; Hellberg, Richard; Eriksson, Joakim, Reduced delay implementation of fourier transform based channelizers and de-channelizers.
  26. Dave Bharat P. ; Jha Niraj K. ; Lakshminarayana Ganesh, Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems.
  27. Mobin Mohammad Shafiul ; Simanapalli Sivanand ; Tate Larry R., Single-cycle accelerator for extremun state search.
  28. Schott, Brian; Parker, Robert, System level applications of adaptive computing (SLAAC) technology.
  29. Stevens,Cameron, System, method and software for static and dynamic programming and configuration of an adaptive computing architecture.
  30. Hunt,Galen C., Tools and techniques for instrumenting interfaces of units of a software program.
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