이 특허에 인용된 특허 (23)

1. Wilson, Sophie, Accessing a test condition for multiple sub-operations using a test register.

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2. Radigan James J. (Sunnyvale CA) Schwartz David A. (Moorpark CA), Activity masking with mask context of SIMD processors.

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3. Panwar Ramesh ; Dakhil Dani Y., Apparatus for enforcing true dependencies in an out-of-order processor.

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4. Artz Ray E. (Apple Valley MN) Martin Richard J. (Eagan MN) Splett Vincent E. (Burnsville MN), Arithmetic computation modifier based upon data dependent operations for SIMD architectures.

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5. Miki Yoshio,JPX ; Shimada Kentaro,JPX ; Hanawa Makoto,JPX, Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition.

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6. Morton Steven G. (Oxford CT), Cellular array processor with individual cell-level data-dependent cell control and multiport input memory.

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7. Branigin Michael H. (151 Ivy Hills Rd. Southbury CT 06488), Computer processor with an efficient means of executing many instructions simultaneously.

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8. Shiell Jonathan H. ; Bartley David H., Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism.

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9. Guttag Karl M. (4015 S. Sandy Ct. Missouri City ; Fort Bend County TX 77459) Read Christopher J. (11807 Burlingame Houston ; Harris County TX 77099) Balmer Keith (6 Salcombe Close Bedfordshire County, Long instruction word controlling plural independent processor operations.

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10. Abdallah Mohammad ; Huff Thomas ; Parrish Gregory C. ; Thakkar Shreekant S., Method and apparatus for efficient vertical SIMD computations.

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11. Petro Anthony M. ; Blomgren James S., Method and apparatus for interruption of carry propagation on partition boundaries.

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12. Prener Daniel A. (Croton NY), Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free acc.

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13. Lavelle Gary (Newtown PA) Lippincott Louis A. (Roebling NJ) Harney Kevin (Brooklyn NY) Rao Dinesh G. (Rancho Cordova CA), Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service ro.

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14. Chan Kin Shing, Method and system for buffering condition code data in a data processing system having out-of-order and speculative inst.

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15. Wilson, Sophie, Method and system for executing conditional instructions using a test register address that points to a test register from which a test code is selected.

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16. Hsu Wei Chung, Method and system for optimizing code.

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17. Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.

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18. Blaner Bartholomew (Underhill Center VT) Larsen Larry D. (Raleigh NC), Multiple condition code branching system in a multi-processor environment.

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19. Yung Robert, Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions.

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20. Natarajan Seshan ; Laurence R. Simar, Jr. ; Reid E. Tatge ; Alan L. Davis, Processor with conditional execution of every instruction.

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21. Wilson,Sophie, System and method for selectively controlling operations in lanes.

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22. Palanca Salvador ; Pentkovski Vladimir M. ; Kuttuva Suresh N. ; Mosur Praveen B., System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data.

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23. Terada Koichi,JPX ; Kojima Keiji,JPX ; Fujikawa Yoshifumi,JPX ; Nojiri Tohru,JPX ; Nishioka Kiyokazu,JPX, VLIW system with predicated instruction execution for individual instruction fields.

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