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Energy storage and control system for a vehicle electrified drivetrain

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B60K-001/04
출원번호 US-0059187 (2008-03-31)
등록번호 US7984776 (2011-07-12)
발명자 / 주소
  • Sastry, Ann M.
  • Beyer, James H.
출원인 / 주소
  • The Regents of the University of Michigan
대리인 / 주소
    Ogawa P.C.
인용정보 피인용 횟수 : 55  인용 특허 : 8

초록

A system for supplying electrical energy to a partial or a total electrified drivetrain of a vehicle, the system may include an energy storage system having an energy storage system output that is excess of an operating voltage of the electrified drivetrain. A first converter having an input coupled

대표청구항

We claim: 1. A system for supplying electrical energy to a partial or a total electrified drivetrain of a vehicle, the system comprising:an energy storage system having an energy storage system output, the energy storage system output having voltage in excess of a operating voltage of the electrifie

이 특허에 인용된 특허 (8)

  1. Cox, Michael; Bertness, Kevin I., Energy management system for automotive vehicle.
  2. Geis, Everett R., Hybrid electric vehicle DC power generation system.
  3. Kumar,Ajith Kuttannair; Young,Henry Todd, Hybrid energy off highway vehicle propulsion circuit.
  4. Nakanowatari, Jun, Hybrid vehicle employing hybrid system.
  5. King Robert Dean ; DeDoncker Rik Wivina Anna Adelson, Power electronic interface circuits for batteries and ultracapacitors in electric vehicles and battery storage systems.
  6. Oyobe, Hichirosai; Ishikawa, Tetsuhiro; Minezawa, Yukihiro, Power output apparatus and vehicle having the same.
  7. Laeuffer, Jacques Augustin, Power transmission method and device for a motor vehicle comprising a heat engine and at least one electric machine.
  8. Pascual Cesar ; Krein Philip T., Switched capacitor system for automatic battery equalization.

이 특허를 인용한 특허 (55)

  1. Kumar, Tanmay, Amorphous silicon RRAM with non-linear device and operation.
  2. Kuo, Harry; Nazarian, Hagop; Nguyen, San Thanh, Capacitive discharge programming for two-terminal memory cells.
  3. Jo, Sung Hyun, Conductive path in switching material in a resistive random access memory device and control.
  4. Jo, Sung Hyun; Lu, Wei, Device switching using layered device structure.
  5. Jo, Sung Hyun; Lu, Wei, Device switching using layered device structure.
  6. Jo, Sung Hyun; Lu, Wei, Device switching using layered device structure.
  7. Maxwell, Steven Patrick, Electrode structure for a non-volatile memory device and method.
  8. Baudesson, Philippe; Grbovic, Petar; Le Moigne, Philippe, Energy-recovery device in a variable speed drive.
  9. Asnaashari, Mehdi; Nazarian, Hagop; Nguyen, Sang, Field programmable gate array utilizing two-terminal non-volatile memory.
  10. Nazarian, Hagop; Nguyen, Sang Thanh; Kumar, Tanmay, Field programmable gate array utilizing two-terminal non-volatile memory.
  11. Nazarian, Hagop; Nguyen, Sang Thanh; Kumar, Tanmay, Field programmable gate array utilizing two-terminal non-volatile memory.
  12. Nazarian, Hagop; Jo, Sung Hyun, Filamentary based non-volatile resistive memory device and method.
  13. Nazarian, Hagop; Jo, Sung Hyun, Filamentary based non-volatile resistive memory device and method.
  14. Jo, Sung Hyun, Guided path for forming a conductive filament in RRAM.
  15. Jo, Sung Hyun, Guided path for forming a conductive filament in RRAM.
  16. Jo, Sung Hyun, Hereto resistive switching material layer in RRAM device and method.
  17. Jo, Sung Hyun, Hetero resistive switching material layer in RRAM device and method.
  18. Jo, Sung Hyun, Hetero-switching layer in a RRAM device and method.
  19. Jo, Sung Hyun, Hetero-switching layer in a RRAM device and method.
  20. Nguyen, Sang; Nazarian, Hagop, High operating speed resistive random access memory.
  21. Jo, Sung Hyun; Nazarian, Hagop; Lu, Wei, Interface control for improved switching in RRAM.
  22. Sun, Xin; Jo, Sung Hyun; Kumar, Tanmay, Low temperature P+ polycrystalline silicon material for non-volatile memory device.
  23. Herner, Scott Brad, Low temperature fabrication method for a three-dimensional memory device and structure.
  24. Nazarian, Hagop; Jo, Sung Hyun; Lu, Wei, Memory array architecture with two-terminal memory cells.
  25. Lu, Wei, Method and structure of monolithically integrated IC and resistive memory using IC foundry-compatible processes.
  26. Maxwell, Steven Patrick; Jo, Sung-Hyun; Herner, Scott Brad, Method for silver deposition for a non-volatile memory device.
  27. Gee, Harry Yue; Maxwell, Steven Patrick; Vasquez, Jr., Natividad; Clark, Mark Harold, Methods for fabricating resistive memory device switching material using ion implantation.
  28. Narayanan, Sundar; Maxwell, Steve; Vasquez, Jr., Natividad; Gee, Harry Yue, Monolithically integrated resistive memory using integrated-circuit foundry compatible processes.
  29. Narayanan, Sundar; Maxwell, Steve; Vasquez, Jr., Natividad; Gee, Harry Yue, Monolithically integrated resistive memory using integrated-circuit foundry compatible processes.
  30. Jo, Sung Hyun; Kim, Kuk-Hwan; Kumar, Tanmay, Noble metal / non-noble metal electrode for RRAM applications.
  31. Nazarian, Hagop; Nguyen, Sang, Non-volatile memory with overwrite capability and low write amplification.
  32. Herner, Scott Brad, On/off ratio for non-volatile memory device and method.
  33. Herner, Scott Brad, On/off ratio for nonvolatile memory device and method.
  34. Herner, Scott Brad, Pillar structure for memory device and method.
  35. Lu, Wei; Jo, Sung Hyun, Rectified switching of two-terminal memory via real time filament formation.
  36. Maxwell, Steven Patrick; Jo, Sung Hyun, Reduced diffusion in metal electrode for two-terminal memory.
  37. Kulatunga, N. Athula, Regenerative braking method.
  38. Jo, Sung Hyun; Nazarian, Hagop, Resistive RAM with preferental filament formation region and methods.
  39. Nazarian, Hagop; Kumar, Tanmay; Jo, Sung Hyun, Resistive memory cell with solid state diode.
  40. Jo, Sung Hyun; Kim, Kuk-Hwan; Kumar, Tanmay, Resistive memory device and fabrication methods.
  41. Lu, Wei, Resistive memory using SiGe material.
  42. Jo, Sung Hyun; Kim, Kuk-Hwan, Resistive random access memory with non-linear current-voltage relationship.
  43. Jo, Sung Hyun, Resistor structure for a non-volatile memory device and method.
  44. Herner, Scott Brad; Vasquez, Natividad, Selective removal method and structure of silver in resistive switching device for a non-volatile memory device.
  45. Herner, Scott Brad, Silver interconnects for stacked non-volatile memory device and method.
  46. Herner, Scott Brad, Stackable non-volatile resistive switching memory device.
  47. Herner, Scott Brad, Stackable non-volatile resistive switching memory device and method of fabricating the same.
  48. Gee, Harry Yue; Clark, Mark Harold; Maxwell, Steven Patrick; Jo, Sung Hyun; Vasquez, Jr., Natividad, Sub-oxide interface layer for two-terminal memory.
  49. Lu, Wei; Jo, Sung Hyun, Switching device having a non-linear element.
  50. Lu, Wei; Jo, Sung Hyun; Nazarian, Hagop, Switching device having a non-linear element.
  51. Herner, Scott Brad, Thin film transistor steering element for a non-volatile memory device.
  52. Jo, Sung Hyun; Bettinger, Joanna; Liu, Xianliang, Three-dimensional oblique two-terminal memory with enhanced electric field.
  53. Jo, Sung Hyun; Kim, Kuk-Hwan; Bettinger, Joanna, Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects.
  54. Jo, Sung Hyun; Kim, Kuk-Hwan; Bettinger, Joanna, Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects.
  55. Jo, Sung Hyun; Herner, Scott Brad, Two terminal resistive switching device structure and method of fabricating.
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