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Automatic quality testing of multimedia rendering by software drivers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/319
출원번호 US-0736186 (2007-04-17)
발명자 / 주소
  • de Waal, Abraham B.
  • Diard, Franck R.
출원인 / 주소
  • NVIDIA Corporation
대리인 / 주소
    Patterson & Sheridan, LLP
인용정보 피인용 횟수 : 2  인용 특허 : 45

초록 ▼

A method and system for automatically verifying the quality of multimedia rendering are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of directing a command intended for a first driver to both the first driver and a second driver in pa

대표청구항 ▼

We claim: 1. A method for verifying data from a multimedia application, the method comprising:directing a command issued by the multimedia application and intended for a first driver to the first driver executed by a unit;directing, in parallel, the command intended for the first driver to a second

이 특허에 인용된 특허 (45)

  1. So John Ling Wing, Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second.
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  2. Vorbach Martin Andreas,DEX ; Munch Robert Markus,DEX, Dynamically reconfigurable data processing system.
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  4. Trimberger Stephen M., Field programmable gate array having programming instructions in the configuration bitstream.
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  7. Martin Vorbach DE; Robert Munch DE, I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures.
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  8. Vorbach Martin,DEX ; Munch Robert,DEX, I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures.
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  9. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
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  10. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Integrated processor and programmable data path chip for reconfigurable computing.
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  11. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
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  12. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
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  13. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  14. Master Paul L. ; Hatley William T. ; Scheuermann II Walter J. ; Goodman Margaret J., Method and apparatus for adaptable digital protocol processing.
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  15. Cummings Mark R., Method and apparatus for communicating information.
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  17. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
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  18. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  19. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
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  20. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
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  21. Haatainen, Niko; Kivinen, Tero; Kukkonen, Jussi; Ylonen, Tatu, Method for intercepting network packets in a computing device.
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  22. Harrison David A. ; Silver Joshua M. ; Soe Soren T., Method for programming complex PLD having more than one function block type.
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  23. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
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  24. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
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  25. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
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  26. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
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  27. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
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  28. Alfieri,Robert A.; Hicok,Gary D.; Sidenblad,Paul J.; Parris,Mark A., Network processing pipeline chipset for routing and host packet processing.
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  29. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
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  30. Risan, Hank; Fitzgerald, Edward Vincent, Preventing unauthorized distribution of media content within a global network.
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  31. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
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  35. Vorbach,Martin, Reconfigurable sequencer structure.
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  36. Trimberger Stephen M., Reprogrammable instruction set accelerator.
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  37. Vorbach,Martin; Bretz,Daniel, Router.
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  40. Kopp Randall L. (Irvine CA) Johnson S. Val (Anaheim CA), Single-chip self-configurable parallel processor.
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  41. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
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  42. Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
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  43. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
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  44. Agrawal Prathima ; Cravatts Mark Robert ; Trotter John Andrew ; Srivastava Mani Bhushan, Wireless adapter architecture for mobile computing.
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  45. Athanas Peter ; Bittner ; Jr. Ray A., Worm-hole run-time reconfigurable processor field programmable gate array (FPGA).
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이 특허를 인용한 특허 (2)

  1. Nash, Charlotte L.; Upton, Stephen J.; Waddling, David R., Diagnosing graphics display problems.
    상세보기
  2. Fuse, Hiroshi, Information processing apparatus and method therefor.
    상세보기

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