초록 ▼

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

대표청구항 ▼

What is claimed is: 1. A chip comprising:a silicon substrate;a transistor in or on said silicon substrate;a first metal layer over said silicon substrate;a second metal layer over said first metal layer and over said silicon substrate;a dielectric layer between said first and second metal layers;a c

What is claimed is: 1. A chip comprising:a silicon substrate;a transistor in or on said silicon substrate;a first metal layer over said silicon substrate;a second metal layer over said first metal layer and over said silicon substrate;a dielectric layer between said first and second metal layers;a contact pad over said silicon substrate;a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a silicon nitride, wherein a first opening in said passivation layer is over a first contact point of said contact pad, and said first contact point is at a bottom of said first opening;a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 1 and 100 micrometers, wherein a second opening in said first polymer layer is over said first contact point;a metallization structure on said first contact point, in said second opening and on said first polymer layer, wherein said metallization structure comprises electroplated gold in said second opening and over said first polymer layer; anda second polymer layer on said metallization structure, wherein a third opening in said second polymer layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said third opening, wherein said second contact point is connected to said first contact point through said second opening, wherein said second contact point is not vertically over said first contact point.