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Monolithically integrated semiconductor materials and devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B32B-009/04
출원번호 US-0591333 (2006-11-01)
등록번호 US8012592 (2011-08-23)
발명자 / 주소
  • Fitzgerald, Eugene A.
출원인 / 주소
  • Massachuesetts Institute of Technology
대리인 / 주소
    Wolf, Greenfield & Sacks, P.C.
인용정보 피인용 횟수 : 4  인용 특허 : 29

초록

Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substra

대표청구항

What is claimed is: 1. A semiconductor structure comprising:a silicon substrate;a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon, and wher

이 특허에 인용된 특허 (29)

  1. Francois J. Henley ; Michael A. Brayan ; William G. En, Cleaving process to fabricate multilayered substrates using low implantation doses.
  2. Francois J. Henley ; Nathan W. Cheung, Controlled cleavage thin film separation process using a reusable substrate.
  3. Henley, Francois J.; Cheung, Nathan W., Controlled cleaving process.
  4. Fitzgerald Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
  5. Fitzgerald Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
  6. Hsu,Louis Lu Chen; Mandelman,Jack A., Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same.
  7. Nathan W. Cheung ; Francois J. Henley, Generic layer transfer methodology by controlled cleavage process.
  8. Henley, Francois J.; Cheung, Nathan W., Gettering technique for wafers made using a controlled cleaving process.
  9. Marx Diethard,JPX ; Kawazu Zempei,JPX ; Hayafuji Norio,JPX, Heteroepitaxial semiconductor device including silicon substrate, GaAs layer and GaN layer #13.
  10. Francois J. Henley ; Michael A. Bryan ; William G. En, High temperature implant apparatus.
  11. Cohen,Guy Moshe; Saenger,Katherine L., Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization.
  12. Lee Denny Lap Yen, Image capture device using a secondary electrode.
  13. Legoues Francoise Kolmer ; Meyerson Bernard Steele, Low defect density/arbitrary lattice constant heteroepitaxial layers.
  14. Fitzgerald, Eugene A., Low threading dislocation density relaxed mismatched epilayers without high temperature growth.
  15. Fitzgerald, Eugene A., Low threading dislocation density relaxed mismatched epilayers without high temperature growth.
  16. Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Xie Ya-Hong (Flemington NJ), Method for making low defect density semiconductor heterostructure and devices made thereby.
  17. Fitzgerald, Eugene A., Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits.
  18. Murthy, Anand; Soman, Ravindra; Boyanov, Boyan, Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer.
  19. Fitzgerald, Eugene A., Monolithically integrated light emitting devices.
  20. Speyer,Chris; Moore,William E., Optical isolator device, and method of making same.
  21. Henley Francois J. ; Cheung Nathan W., Pre-semiconductor process implant and post-process film separation.
  22. Bruel Michel,FRX, Process for the manufacture of thin films of semiconductor material.
  23. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  24. Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Monroe Donald P. (Berkeley Heights NJ) Silverman Paul J. (Millburn NJ) Xie Ya-Hong (Fl, Semiconductor heterostructure devices with strained semiconductor layers.
  25. Fitzergald, Eugene A., Silicon wafer with embedded optoelectronic material for monolithic OEIC.
  26. Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.
  27. Chu,Jack O.; Dehlinger,Gabriel K.; Grill,Alfred; Koester,Steven J.; Ouyang,Qiging; Schaub,Jeremy D., Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector.
  28. Fitzgerald Eugene A. ; Samavedam Srikanth B., Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon.
  29. Yap, Daniel, Waveguide-bonded optoelectronic devices.

이 특허를 인용한 특허 (4)

  1. Cai, Jin; Chan, Kevin K.; D'Emic, Christopher P.; Hekmatshoartabari, Bahman; Ning, Tak H.; Park, Dae-Gyu, Germanium lateral bipolar junction transistor.
  2. Cai, Jin; Chan, Kevin K.; D'Emic, Christopher P.; Hekmatshoartabari, Bahman; Ning, Tak H.; Park, Dae-Gyu, Germanium lateral bipolar junction transistor.
  3. Stamper, Anthony K.; Jain, Vibhor; Camillo-Castillo, Renata A., Integrated CMOS wafers.
  4. Fitzgerald, Eugene A., Monolithic integration of CMOS and non-silicon devices.
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