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Post passivation interconnection schemes on top of the IC chips 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0142825 (2008-06-20)
등록번호 US8013449 (2011-08-23)
발명자 / 주소
  • Lin, Mou-Shiung
  • Chou, Chiu-Ming
  • Chou, Chien-Kang
출원인 / 주소
  • Megica Corporation
대리인 / 주소
    McDermott Will & Emery, LLP
인용정보 피인용 횟수 : 0  인용 특허 : 162

초록 ▼

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thi

대표청구항 ▼

What is claimed is: 1. A chip comprising:a silicon substrate;an ESD circuit on said silicon substrate;an internal circuit on said silicon substrate;a driver, receiver or I/O circuit on said silicon substrate;a dielectric layer over said silicon substrate;a fine-line metallization structure over said

이 특허에 인용된 특허 (162)

  1. Bohr, Mark T., Alternate bump metallurgy bars for power and ground routing.
    상세보기
  2. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
    상세보기
  3. Stewart Roger G. (Neshanic Station NJ) Mazin Moshe (Scotia NY), Apparatus for decoding multiple input lines.
    상세보기
  4. Mou-Shiung Lin TW, Capacitor for high performance system-on-chip using post passivation process structure.
    상세보기
  5. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
    상세보기
  6. Ties Ramcke DE; Lothar Risch DE; Wolfgang Rosner DE, Circuit configuration having at least one nanoelectronic component and method for fabricating the component.
    상세보기
  7. Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.
    상세보기
  8. Cleeves, James M., Contact and via structure and method of fabrication.
    상세보기
  9. Omura Masayoshi,JPX, Damascene wiring with flat surface.
    상세보기
  10. Delgado Jose A. ; McLachlan Craig J., Defect gettering by induced stress.
    상세보기
  11. Hsuan Min Chih,TWX ; Han Charlie,TWX, Direct contact through hole type wafer structure.
    상세보기
  12. Fillion Raymond A. (Niskayuna NY) Wildi Eric J. (Niskayuna NY) Korman Charles S. (Schenectady NY) El-Hamamsy Sayed-Amr (Schenectady NY) Gasworth Steven M. (Glenville NY) DeVre Michael W. (Scotia NY) , Direct stacked and flip chip power semiconductor device structures.
    상세보기
  13. Chen,Hsien Wei, Dummy structures extending from seal ring into active circuit area of integrated circuit chip.
    상세보기
  14. Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX), ESD protection structure using LDMOS diodes with thick copper interconnect.
    상세보기
  15. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Electroless gold plating method for forming inductor structures.
    상세보기
  16. Ohori Tatsuya,JPX ; Hori Tetsurou,JPX, Electronic circuit device with multi-layer wiring.
    상세보기
  17. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Electronic component with die and passive device.
    상세보기
  18. Countryman Roger (Austin TX) Gerosa Gianfranco (Austin TX) Mendez Horacio (Austin TX), Electrostatic discharge protection device.
    상세보기
  19. Williams Richard K. (Cupertino CA) Hille Peter (Darmstadt DEX) Wrathall Robert G. (Scotts Valley CA), Electrostatic discharge protection device for integrated circuit.
    상세보기
  20. Matsumoto Shigeyuki (Atsugi JPX) Ikeda Osamu (Tokyo JPX), Flat semiconductor wiring layers.
    상세보기
  21. Liang Mike, Flip chip bump distribution on die.
    상세보기
  22. Shenoy Jayarama N. ; Findley Paul, Flip chip circuit arrangement with redistribution layer that minimizes crosstalk.
    상세보기
  23. Takada Norimasa (Tokyo JPX), Flip chip type semiconductor device.
    상세보기
  24. Lu, Hsueh-Chung Shelton; Chang, Kenny; Huang, Jimmy, Flip-chip bump arrangement for decreasing impedance.
    상세보기
  25. Hsu, Chi-Hsing, Flip-chip die and flip-chip package substrate.
    상세보기
  26. Wachtler, Kurt P.; Walter, David N.; Mowatt, Larry J., HID land grid array packaged device having electrical and optical interconnects.
    상세보기
  27. Wollesen Donald L. (Saratoga CA), High conductivity interconnection line.
    상세보기
  28. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), High performance interconnect system for an integrated circuit.
    상세보기
  29. Lin Mou-Shiung,TWX, High performance sub-system design and assembly.
    상세보기
  30. Lin, Mou-Shiung, High performance system-on-chip discrete components using post passivation process.
    상세보기
  31. Yamazaki Shunpei,JPX ; Teramoto Satoshi,JPX, Hybrid circuit and electronic device using same.
    상세보기
  32. Mou-Shiung Lin TW, Inductor structure for high performance system-on-chip using post passivation process.
    상세보기
  33. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
    상세보기
  34. Kloen Hendrik K.,NLX ; Huiskamp Lodewijk P.,NLX, Integrated circuit device.
    상세보기
  35. Lamson Michael A. (Van Alstyne TX) Edwards Darvin R. (Dallas TX), Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof.
    상세보기
  36. Staudinger Joseph (Gilbert AZ) Seely Warren L. (Chandler AZ) Patterson Howard W. (Phoenix AZ), Integrated circuit having passive circuit elements.
    상세보기
  37. Fillion Raymond Albert ; Burdick ; Jr. William Edward ; Kolc Ronald Frank ; Rose James Wilson ; Claydon Glenn Scott, Integrated circuit package including window frame.
    상세보기
  38. Efland, Taylor R.; Abbott, Donald C.; Bucksch, Walter; Corsi, Marco; Shen, Chi-Cheong; Erdeljac, John P.; Hutter, Louis N.; Mai, Quang X.; Wagensohner, Konrad; Williams, Charles E.; Buschbom, Milton , Integrated circuit with bonding layer over active circuitry.
    상세보기
  39. Shen Chi-Cheong ; Abbott Donald C. ; Bucksch Walter,DEX ; Corsi Marco ; Efland Taylor Rice ; Erdeljac John P. ; Hutter Louis Nicholas ; Mai Quang ; Wagensohner Konrad,DEX ; Williams Charles Edward, Integrated circuit with bonding layer over active circuitry.
    상세보기
  40. Buynoski, Matthew S., Low dielectric metal silicide lined interconnection system.
    상세보기
  41. Buynoski Matthew S., Low dielectric semiconductor device with rigid lined interconnection system.
    상세보기
  42. Brown Vernon L. ; Magera Yaroslaw A., Metallization and termination process for an integrated circuit chip.
    상세보기
  43. Erdeljac John P. ; Hutter Louis Nicholas ; Khatibzadeh M. Ali ; Arch John Kenneth, Metallization outside protective overcoat for improved capacitors and inductors.
    상세보기
  44. Mistry Addi Burjorji ; Sarihan Vijay ; Kleffner James H. ; Carney George F., Method and apparatus for stress relief in solder bump formation on a semiconductor device.
    상세보기
  45. Nakamura, Yoshitaka; Tamaru, Tsuyoshi; Fukuda, Naoki; Goto, Hidekazu; Asano, Isamu; Aoki, Hideo; Kawakita, Keizo; Yamada, Satoru; Tanaka, Katsuhiko; Sakuma, Hiroshi; Hirasawa, Masayoshi, Method for fabricating semiconductor integrated circuit.
    상세보기
  46. Wakabayashi Takeshi (Hidaka JPX) Suzuki Akira (Musashino JPX) Yokoyama Shigeru (Chofu JPX), Method for forming a bump electrode for a semiconductor device.
    상세보기
  47. Boyd Melissa D. (Corvallis OR), Method for forming a conductive pattern on an integrated circuit.
    상세보기
  48. Lee Jia-Sheng,TWX, Method for forming a thin-film resistor.
    상세보기
  49. Park,Hee Sook, Method for forming contact having low resistivity using porous plug and method for forming semiconductor devices using the same.
    상세보기
  50. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
    상세보기
  51. Lin Mou-Shiung,TWX, Method for forming high performance system-on-chip using post passivation process.
    상세보기
  52. Gansauge Peter (Boeblingen DEX) Kreuter Volker (Schoenaich DEX) Schettler Helmut (Dettenhausen DEX), Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer.
    상세보기
  53. Leung Pak K.,CAX ; Emesh Ismail T.,CAX, Method of adding on chip capacitors to an integrated circuit.
    상세보기
  54. Iadanza, Joseph A., Method of connecting core I/O pins to backside chip I/O pads.
    상세보기
  55. Yamaguchi, Yoshihide; Tenmei, Hiroyuki; Hozoji, Hiroshi; Kanda, Naoya, Method of fabricating a wafer level chip size package utilizing a maskless exposure.
    상세보기
  56. Wu, Kuo-Chien; Chen, Yinan, Method of fabricating contact holes on a semiconductor chip.
    상세보기
  57. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
    상세보기
  58. Dow Stephen (Chandler AZ) Maass Eric C. (Scottsdale AZ) Marlin Bill (Phoenix AZ), Method of making an electronic device having an integrated inductor.
    상세보기
  59. Gocho Tetsuo,JPX, Method of manufacturing a semiconductor device.
    상세보기
  60. Tamaru,Tsuyoshi; Oomori,Kazutoshi; Miura,Noriko; Aoki,Hideo; Oshima,Takayuki, Method of manufacturing a semiconductor device.
    상세보기
  61. Peters Johannes S. (Nijmegen NLX), Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided o.
    상세보기
  62. Brandli Gerold (Aarau CHX) Bachmann Guido (Sempach CHX), Method of manufacturing multi-layer thin film circuits containing integrated thin film resistors.
    상세보기
  63. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
    상세보기
  64. Kie Y. Ahn ; Leonard Forbes, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
    상세보기
  65. Zhao Ji ; Teng Chih Sieh, Methods for making VLSI capacitors and high Q VLSI inductors using metal-filled via plugs.
    상세보기
  66. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.
    상세보기
  67. Bothra Subhas ; Qian Ling Q., Methods for making semiconductor devices having air dielectric interconnect structures.
    상세보기
  68. Cronin John Edward (Milton VT) Howell Wayne John (Williston VT) Kalter Howard Leo (Colchester VT) Marmillion Patricia Ellen (Colchester VT) Palagonia Anthony (Underhill VT) Pierson Bernadette Ann (So, Methods for precise definition of integrated circuit chip edges.
    상세보기
  69. Kim, Sarah E.; Lee, Kevin J.; George, Anna M., Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow.
    상세보기
  70. Chen, Sheng-Hsiung; Chen, Shun Long; Lin, Hungtse, Modified pad for copper/low-k.
    상세보기
  71. Laurent Basteres FR; Ahmed Mhani FR; Fran.cedilla.ois Valentin FR; Jean-Michel Karam FR, Monolithic integrated circuit incorporating an inductive component and process for fabricating such an integrated circuit.
    상세보기
  72. Ahn Kie Y. ; Forbes Leonard, Multichip module with built in repeaters and method.
    상세보기
  73. Ki Jik Lee KR; Jae Min Yu KR, Nonvolatile memory and method for fabricating the same.
    상세보기
  74. Hsuan Min-Chih,TWX ; Liou Fu-Tai,TWX, Package-free bonding pad structure.
    상세보기
  75. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R., Personalization structure for semiconductor devices.
    상세보기
  76. Tung, Francisca, Pillar connections for semiconductor chips and method of manufacture.
    상세보기
  77. Thomas David C. (Wilkes-Barre PA) Wong S. Simon (Ithaca NY), Planar tungsten interconnect with implanted silicon.
    상세보기
  78. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection process and structures.
    상세보기
  79. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  80. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  81. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  82. Mou-Shiung Lin TW; Jin-Yuan Lee TW, Post passivation interconnection schemes on top of the IC chips.
    상세보기
  83. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
    상세보기
  84. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
    상세보기
  85. Hool, Vincent; Long, Jon, Post-passivation thick metal pre-routing for flip chip packaging.
    상세보기
  86. Ghoshal Uttam Shyamalindu, Practical air dielectric interconnections by post-processing standard CMOS wafers.
    상세보기
  87. Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN), Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal.
    상세보기
  88. Quinn ; Daniel J. (Carrollton TX) Mulholland Wayne A. (Plano TX) Bond Robert H. (Carrollton TX) Olla Michael A. (Flower Mound TX) Cupples Jerry S. (Carrollton TX) Tsitovsky Ilya L. (Farmers Branch TX, Process of forming integrated circuits with contact pads in a standard array.
    상세보기
  89. Ubaldo Mastromatteo IT; Fabrizio Ghironi IT; Roberto Aina IT; Mauro Bombonati IT, Process of manufacturing a composite structure for electrically connecting a first body of semiconductor material overlaid by a second body of semiconductor material.
    상세보기
  90. Giannella Piccolo G. (Saratoga CA), Programmable die size continuous array.
    상세보기
  91. Dangelo Carlos (Los Gatos CA), Programmable microsystems in silicon.
    상세보기
  92. Leibovitz Jacques ; Yu Park-Kee ; Zhu Ya Yun ; Cobarruviaz Maria L. ; Swindlehurst Susan J. ; Chang Cheng-Cheng ; Scholz Kenneth D., Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps.
    상세보기
  93. Antol,Joze E.; Seitzer,Philip William; Chesire,Daniel Patrick; Mengel,Rafe Carl; Archer,Vance Dolvan; Gans,Thomas B.; Kook,Taeho; Merchant,Sailesh M., Reinforced bond pad for a semiconductor device.
    상세보기
  94. Kumamoto, Nobuhisa; Samejima, Katsumi, Semiconductor chip and production process therefor.
    상세보기
  95. Hajime Iizuka JP, Semiconductor device.
    상세보기
  96. Naoki Nojiri JP, Semiconductor device.
    상세보기
  97. Takeuchi, Masahiko; Dokan, Takashi, Semiconductor device.
    상세보기
  98. Koike,Hidetoshi, Semiconductor device and manufacturing method thereof.
    상세보기
  99. Ohmori,Kazutoshi; Tamaru,Tsuyoshi; Ohashi,Naohumi; Sato,Kiyohiko; Maruyama,Hiroyuki, Semiconductor device and manufacturing method thereof.
    상세보기
  100. Kikuchi, Hidekazu, Semiconductor device and method for manufacturing.
    상세보기
  101. Hiroyuki Ohta JP; Hideo Miura JP; Kazushige Sato JP; Takeshi Kimura JP; Hiroo Masuda JP, Semiconductor device and method of fabricating same.
    상세보기
  102. Kitamura,Takuya; Sakoh,Takashi, Semiconductor device and method of manufacturing the same.
    상세보기
  103. Koichi Sugiyama JP; Yukio Hosoda JP; Shinichiroh Ikemasu JP, Semiconductor device and method of manufacturing the same.
    상세보기
  104. Kasai, Naoki, Semiconductor device comprising high density integrated circuit having a large number of insulated gate field effect transistors.
    상세보기
  105. Aoki, Yutaki; Mihara, Ichiro; Wakabayashi, Takeshi; Watanabe, Katsumi, Semiconductor device having a barrier layer.
    상세보기
  106. Kim Seong Jin,KRX, Semiconductor device having a bump structure and test electrode.
    상세보기
  107. Aoki, Yutaka, Semiconductor device having a chip size package including a passive element.
    상세보기
  108. Aoyama Masaharu (Fujisawa JPX) Abe Masahiro (Yokohama JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Kitakyushu JPX), Semiconductor device having a multilayer wiring structure using a polyimide resin.
    상세보기
  109. Downey, Susan H.; Miller, James W.; Hall, Geoffrey B., Semiconductor device having a wire bond pad and method therefor.
    상세보기
  110. Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX, Semiconductor device having an element with circuit pattern thereon.
    상세보기
  111. Amishiro Hiroyuki,JPX ; Igarashi Motoshige,JPX, Semiconductor device including a plurality of interconnection layers.
    상세보기
  112. Kunishima, Hiroyuki; Takewaki, Toshiyuki, Semiconductor device including dissimilar element-diffused metal layer and manufacturing method thereof.
    상세보기
  113. Nakanishi Shiro,JPX, Semiconductor device or thin-film transistor manufacturing apparatus and manufacturing method.
    상세보기
  114. Nozaki Masahiko (Hyogo JPX), Semiconductor device structure including multiple interconnection layers with interlayer insulating films.
    상세보기
  115. Yamasaki Kyoji,JPX ; Asakura Mikio,JPX ; Yamauchi Tadaaki,JPX, Semiconductor device structured to be less susceptible to power supply noise.
    상세보기
  116. Fukuzumi,Yoshiaki, Semiconductor device using high-dielectric-constant material and method of manufacturing the same.
    상세보기
  117. Usui,Takamasa, Semiconductor device using insulating film of low dielectric constant as interlayer insulating film.
    상세보기
  118. Yutaka Aoki JP; Hiroshi Takenaka JP; Ichiro Mihara JP, Semiconductor device which prevents leakage of noise generated in a circuit element forming area and which shields against external electromagnetic noise.
    상세보기
  119. Yoshihisa Matsubara JP, Semiconductor device with alloy film between barrier metal and interconnect.
    상세보기
  120. Oda,Noriaki, Semiconductor device with bonding pad support structure.
    상세보기
  121. Uchikoshi,Ken; Suwanai,Naokatsu; Tachigami,Atsushi; Hotta,Katsuhiko; Sahara,Masashi; Sato,Kazuhiko, Semiconductor device with guard rings that are formed in each of the plural wiring layers.
    상세보기
  122. Matsuki Hirohisa,JPX ; Kado Kenichi,JPX ; Watanabe Eiji,JPX ; Imamura Kazuyuki,JPX ; Yurino Takahiro,JPX, Semiconductor device with pad structure.
    상세보기
  123. Anzai,Noritaka, Semiconductor device with signal line having decreased characteristic impedance.
    상세보기
  124. Misawa Kaori,JPX ; Ishihara Hiroyasu,JPX ; Mizuhara Hideki,JPX, Semiconductor devices with means to reduce contamination.
    상세보기
  125. Ishii Kazutoshi,JPX ; Inoue Naoto,JPX ; Maemura Koushi,JPX ; Nakanishi Shoji,JPX ; Kojima Yoshikazu,JPX ; Kadoi Kiyoaki,JPX ; Akiba Takao,JPX ; Moya Yasuhiro,JPX ; Kuhara Kentaro,JPX, Semiconductor dicing and assembling method.
    상세보기
  126. Kato, Katsuhiro, Semiconductor integrated circuit device.
    상세보기
  127. Saito,Tatsuyuki; Ohashi,Naohumi; Imai,Toshinori; Noguchi,Junji; Tamaru,Tsuyoshi, Semiconductor integrated circuit device.
    상세보기
  128. Satonaka Koichiro (Fuchu JA), Semiconductor integrated circuit device.
    상세보기
  129. Shinozaki, Masao; Nishimoto, Kenji; Akioka, Takashi; Kohara, Yutaka; Asari, Sanae; Miyata, Shusaku; Nakazato, Shinji, Semiconductor integrated circuit device.
    상세보기
  130. Ohashi Naofumi,JPX ; Yamaguchi Hizuru,JPX ; Noguchi Junji,JPX ; Owada Nobuo,JPX, Semiconductor integrated circuit device and fabrication process thereof.
    상세보기
  131. Fukuda Takuya,JPX ; Ohji Yuzuru,JPX ; Kobayashi Nobuyoshi,JPX, Semiconductor integrated circuit device and method of manufacturing same.
    상세보기
  132. Tokunaga,Shinya; Furuya,Shigeki; Hinatsu,Yuuji, Semiconductor integrated circuit device and method of producing the same.
    상세보기
  133. Makoto Yoshida JP; Katsuyuki Asaka JP; Toshihiko Takakura JP, Semiconductor integrated circuit device and process for manufacturing the same.
    상세보기
  134. Meguro Hideo (Tachikawa TX JPX) Yoshiura Yoshiaki (Irving TX) Itagaki Tatsuo (Hinode JPX) Uchida Ken (Higashiyamato JPX) Satoh Tsuneo (Tachikawa JPX) Ichihara Seiichi (Hachioji TX JPX) Nagasawa Koich, Semiconductor integrated circuit device and process for producing the same.
    상세보기
  135. Tomita, Kenichi; Inoue, Tomotoshi; Terada, Toshiyuki, Semiconductor integrated circuit device having a hollow multi-layered lead structure.
    상세보기
  136. Aomura Kunio (Tokyo JPX), Semiconductor integrated circuit device including element for monitoring characteristics of the device.
    상세보기
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