최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0036308 (2008-02-25) |
등록번호 | US8022545 (2011-09-06) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 3 인용 특허 : 502 |
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabli
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
What is claimed is: 1. A semiconductor chip comprising:a silicon substrate;multiple transistors on said silicon substrate;a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal
What is claimed is: 1. A semiconductor chip comprising:a silicon substrate;multiple transistors on said silicon substrate;a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal layer over said silicon substrate and over said first metal layer, a first metal interconnect over said silicon substrate, a second metal interconnect over said silicon substrate, a third metal interconnect over said silicon substrate and between said first and second metal interconnects, a fourth metal interconnect over said silicon substrate and between said third and second metal interconnects, and a fifth metal interconnect over said silicon substrate, wherein said third metal interconnect comprises a portion spaced apart from said first and fourth metal interconnects, and wherein said fourth metal interconnect comprises a portion spaced apart from said second and third metal interconnects, wherein said first metallization structure comprises electroplated copper;a dielectric layer between said first and second metal layers;a separating layer over said first metallization structure, over said dielectric layer and on said third and fourth metal interconnects, wherein said first, second, third, fourth and fifth metal interconnects are provided by a topmost metal layer under said separating layer, wherein said separating layer comprises a nitride layer, wherein a first opening in said separating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, wherein a second opening in said separating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, and wherein a third opening in said separating layer is over a third contact point of said fifth metal interconnect, and said third contact point is at a bottom of said third opening;a polymer layer on said separating layer and over said third and fourth metal interconnects, wherein said polymer layer has a thickness between 2 and 30 micrometers, wherein a fourth opening in said polymer layer is over said first contact point and over said first opening, wherein a fifth opening in said polymer layer is over said second contact point and over said second opening, and wherein a sixth opening in said polymer layer is over said third contact point and over said third opening;a second metallization structure on said polymer layer, over said separating layer, vertically over said third and fourth metal interconnects and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure is connected to said first contact point through said first and fourth openings, and connected to said second contact point through said second and fifth openings, wherein said second metallization structure comprises electroplated copper in said first, second, fourth and fifth openings and over said polymer layer, wherein said second metallization structure contacts a sidewall of said first opening, a sidewall of said second opening, a sidewall of said fourth opening and a sidewall of said fifth opening; anda third metallization structure on said polymer layer, over said separating layer and on said third contact point, wherein said third metallization structure on said polymer layer comprises a portion spaced apart from said second metallization structure on said polymer layer, wherein said third metallization structure is connected to said third contact point through said third and sixth openings, wherein said third metallization structure comprises electroplated copper in said third and sixth openings and over said polymer layer, wherein said third metallization structure contacts a sidewall of said third opening and a sidewall of said sixth opening.
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