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특허 상세정보

Top layers of metal for high performance IC's

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-023/485   
미국특허분류(USC) 257/758; 257/691; 257/760; 257/E21575
출원번호 US-0036308 (2008-02-25)
등록번호 US8022545 (2011-09-06)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    McDermott Will & Emery, LLP
인용정보 피인용 횟수 : 3  인용 특허 : 502
초록

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

대표
청구항

What is claimed is: 1. A semiconductor chip comprising:a silicon substrate;multiple transistors on said silicon substrate;a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer over said silicon substrate, a second metal layer over said silicon substrate and over said first metal layer, a first metal interconnect over said silicon substrate, a second metal interconnect over said silicon substrate, a third metal interconnect over said silicon substrate and between said first an...

이 특허에 인용된 특허 (502)

  1. Haller Theodore R. (Scotia NY) Wojnarowski Robert J. (Ballston Lake NY). Adaptive lithography in a high density interconnect structure whose signal layers have fixed patterns. USP1994105357403.
  2. Hsia Liang Choo,TWX ; Chang Thomas Tong Long. Additive metalization using photosensitive polymer as RIE mask and part of composite insulator. USP1998105827780.
  3. Bohr, Mark T.. Alternate bump metallurgy bars for power and ground routing. USP2003116653563.
  4. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects. USP2002046376353.
  5. Burns Stanley G. ; Gruber Carl ; Shanks Howard R. ; Constant Alan P. ; Landin Allen R. ; Schmidt David H.. Amorphous silicon on insulator VLSI circuit structures. USP1998045742075.
  6. Goel Atul ; Chen Yaw-Hwang ; Spencer John R.. Ancillary pads for on-circuit array probing composed of I/O and test pads. USP1998115838023.
  7. Hasegawa Masayasu (Kyoto JPX) Nishikawa Hideo (Ibaraki JPX) Yoshida Kayoko (Takatsuki JPX). Antibacterial and antifungal composition. USP1980124242336.
  8. Higgins ; III Leo M. (Austin TX). Area array semiconductor device having a lid with functional contacts. USP1994035291062.
  9. Malinovich Yacov,ILX ; Koltin Ephie,ILX. Backside illuminated image sensor. USP2001016169319.
  10. Sasaki Masatomi (Ashigarakami JPX) Sakakibara Hiroki (Ashigarakami JPX) Saruhashi Makoto (Ashigarakami JPX) Tategami Shinichi (Ashigarakami JPX). Biocompatible material for medical apparatus comprising hydrophobically bound oil-soluble vitamin. USP1996025489303.
  11. Chittipeddi Sailesh ; Ryan Vivian. Bond pad design for integrated circuits. USP1999115986343.
  12. Lin Shi-Tron,TWX. Bond pad with pad edge strengthening structure. USP2001106306749.
  13. Takiar Hem P. (San Jose CA) George Thomas (Albany CA). Bonding pad interconnection structure. USP1988024723197.
  14. Ichikawa Matsuo,JPX. Bonding pad structures for semiconductor integrated circuits. USP1998025719448.
  15. Sunil D. Mehta. Borderless vias on bottom metal. USP2002036362527.
  16. Sunil D. Mehta. Borderless vias on bottom metal. USP2002106472308.
  17. Chun Heung-Sup,KRX. Bottom lead semiconductor chip package. USP2000036043430.
  18. Fan, Yang-Tung; Chu, Cheng-Yu; Fan, Fu-Jier; Lin, Shih-Jane; Peng, Chiou-Shian; Chen, Yen-Ming; Lin, Kuo-Wei. Bumping process to increase bump height and to create a more robust bump structure. USP2003086605524.
  19. Leung Pak K. (Kanata CAX) Emesh Ismail T. (Cumberland CAX). Capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an int. USP1996105563762.
  20. Mou-Shiung Lin TW. Capacitor for high performance system-on-chip using post passivation process structure. USP2002126489647.
  21. Bertolet Allan ; Fiore James ; Gramatzki Eberhard. Chip design process for wire bond and flip-chip package. USP2001036204074.
  22. Greco Stephen E. (LaGrangeville NY) Srikrishnan Kris V. (Wappingers Falls NY). Chip interconnection having a breathable etch stop layer. USP1994125371047.
  23. Peter Elenius ; Harry Hollack. Chip scale package using large ductile solder balls. USP2002086441487.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng. Chip structure and process for forming the same. USP2004066756295.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng. Chip structure and process for forming the same. USP2004076762115.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng. Chip structure and process for forming the same. USP2004096798073.
  27. Thomas H. DiStefano ; John W. Smith. Chip with internal signal routing in external element. USP2002046365975.
  28. Harada Masahide (Yokohamashi JPX) Ando Akihiro (Yokohama JPX) Satoh Ryohei (Yokohama JPX) Yabushita Akira (Yokohama JPX) Kanda Naoya (Yokosuka JPX) Horikoshi Kazuhiko (Kawasaki JPX). Circuit board with metal layer for solder bonding and electronic circuit device employing the same. USP1995125476726.
  29. Takeyuki Itabashi JP. Circuit board, a method for manufacturing same, and a method of electroless plating. USP2002046370768.
  30. Chang Ted (Mountain View CA). Circuit routing structure using fewer variable masks. USP1996125581098.
  31. Cerny Charles L. A. ; Bozada Christopher A. ; DeSalvo Gregory C. ; Ebel John L. ; Dettmer Ross W. ; Gillespie James K. ; Havasy Charles K. ; Jenkins Thomas J. ; Nakano Kenichi ; Pettiford Carl I. ; Q. Complementary heterostructure integrated single metal transistor apparatus. USP2001046222210.
  32. Feilchenfeld Natalie Barbara ; Fuerniss Stephen Joseph ; Gaynes Michael Anthony ; Pierson Mark Vincent ; Hoontrakul Pat. Component carrier with raised bonding sites. USP2000116150726.
  33. Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX). Configuration and method for positioning semiconductor device bond pads using additional process layers. USP1995015384488.
  34. Cyrell Alexander. Continuously adjustable surface mounting system. USP1999085934636.
  35. Murdeshwar Nikhil M.. Control of size and heat affected zone for fine pitch wire bonding. USP2001076267290.
  36. Farrar, Paul A.. Copper metallurgy in integrated circuits. USP2003096614099.
  37. Mitwalsky Alexander R. ; Chen Tze-Chiang. Crack stops. USP2000026025639.
  38. Mitwalsky Alexander R. ; Chen Tze-Chiang. Crack stops. USP1998085789302.
  39. Woolley Barry,GBX. Cutting insert. USP1999085934844.
  40. Chen Sen-Fu,TWX ; Wu Jie-Shing,TWX ; Chen Fang-Cheng,TWX ; Lee Tsung-Tser,TWX. Damage free passivation layer etching process. USP1999126001538.
  41. Patwa Nital ; Brown-West Jayne. Decoupling capacitor for integrated circuit signal driver. USP1999035883423.
  42. Delgado Jose A. ; McLachlan Craig J.. Defect gettering by induced stress. USP1999075929508.
  43. Agarwal, Vishnu K.. Device and method for protecting against oxidation of a conductive layer in said device. USP2003086607975.
  44. Chittipeddi Sailesh ; Cochran William T. ; Smooha Yehuda. Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein. USP1999105965903.
  45. Shroff, Mehul; Benard, Gerald G.; Grigg, Philip. Dielectric between metal structures and method therefor. USP2003066583043.
  46. Russell, Steven W.; Lee, Wei William. Dielectric layer liner for an integrated circuit structure. USP2004086774489.
  47. Fillion Raymond A. (Niskayuna NY) Wildi Eric J. (Niskayuna NY) Korman Charles S. (Schenectady NY) El-Hamamsy Sayed-Amr (Schenectady NY) Gasworth Steven M. (Glenville NY) DeVre Michael W. (Scotia NY) . Direct stacked and flip chip power semiconductor device structures. USP1996075532512.
  48. Cleeves James M. (Redwood City CA). Disposable posts for self-aligned non-enclosed contacts. USP1997075652182.
  49. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S.. Dissolvable dielectric method. USP1999095953626.
  50. Nonaka Osamu,JPX. Distance measurement device. USP1999115986764.
  51. Elkmann Norbert,DEX ; Schmucker Ulrich,DEX ; Scharfe Holger,DEX ; Schoop Christian,DEX ; Kubbe Ingo,DEX. Drive device for moving a robot or vehicle on flat, inclined or curved surfaces, particularly of a glass construction a. USP1999095959424.
  52. Chittipeddi, Sailesh; Cochran, William Thomas; Smooha, Yehuda. Dual damascene bond pad structure for lowering stress and allowing circuitry under pads. USP2005016838769.
  53. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M.. Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer. USP2000036037664.
  54. Kang-Cheng Lin TW. Dual damascene process and structure with dielectric barrier layer. USP2002026348733.
  55. Yeh Wen-Kuan,TWX. Dual damascene process using low-dielectric constant materials. USP2000096114233.
  56. Wetzel Jeffrey Thomas. Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation. USP2000116143646.
  57. Agarwala,Birendra N.; Coker,Eric M.; Correale, Jr.,Anthony; Rathore,Hazara S.; Sullivan,Timothy D.; Wachnik,Richard A.. Dual-damascene metallization interconnection. USP2007057224063.
  58. Chang Chung-Chen (Los Altos CA) Wu Cheng C. (San Jose CA). EPROM fabrication process. USP1989054830974.
  59. Yuan Lee Chung,TWX. ESD protection circuit located under protected bonding pad. USP1998115838043.
  60. Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX). ESD protection structure using LDMOS diodes with thick copper interconnect. USP1995115468984.
  61. Trask Philip A. (Laguna Hills CA) Pillai Vincent A. (Irvine CA) Gierhart Thomas J. (Fountain Valley CA). Electrical interconnection substrate with both wire bond and solder contacts. USP1994055311404.
  62. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY). Electroless deposition for IC fabrication. USP1992125169680.
  63. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX. Electroless gold plating method for forming inductor structures. USP2000026030877.
  64. Mercer Frank W. (Belmont CA) Goodman Timothy D. (Redwood City CA) Lau Aldrich N. K. (Palo Alto CA) Vo Lanchi P. (San Jose CA) Sovish Richard C. (Los Altos CA). Electronic articles containing a fluorinated poly(arylene ether) dielectric. USP1992055114780.
  65. Moriwaki Nobushige,JPX ; Nishiyama Shigeki,JPX. Electronic component. USP2001076259593.
  66. Wojnarowski Robert John. Electronic device pad relocation, precision placement, and packaging in arrays. USP1999035888884.
  67. Ushio Jiro (Yokohama JPX) Miyazawa Osamu (Yokosuka JPX) Tomizawa Akira (Yokohama JPX) Yokono Hitoshi (Ibaraki JPX) Kanda Naoya (Yokohama JPX) Matsuura Naoko (Yokohama JPX) Ando Setsuo (Kawasaki JPX) . Electronic device plated with gold by means of an electroless gold plating solution. USP1990104963974.
  68. Lewis Robert L. (Apalachin NY) Sebesta Robert D. (Endicott NY) Waits Daniel M. (Vestal NY). Electronic package with multilevel connections. USP1997035612573.
  69. Countryman Roger (Austin TX) Gerosa Gianfranco (Austin TX) Mendez Horacio (Austin TX). Electrostatic discharge protection device. USP1996055514892.
  70. Williams Richard K. (Cupertino CA) Hille Peter (Darmstadt DEX) Wrathall Robert G. (Scotts Valley CA). Electrostatic discharge protection device for integrated circuit. USP1996085545909.
  71. Bhattacharyya Arup ; Leidy Robert K.. Embedded power and ground plane structure. USP1999025874778.
  72. Joshi Rajiv Vasant ; Reohr William Robert. Embedded thermal conductors for semiconductor chips. USP1999095955781.
  73. Camplin Harry R. (Marine on the St. Croix MN) Shackleton Michael A. (San Jose CA). Engine air cleaner. USP1981124303423.
  74. Farrar,Paul A.. Etch stop in damascene interconnect structure and method of making. USP2006067057289.
  75. Galloway Terry R.. Extended bond pads with a plurality of perforations. USP1998075783868.
  76. Jacobs Scott L. (Apex NC). Extended integration semiconductor structure with wiring layers. USP1991105055907.
  77. Rostoker Michael D. ; Pasch Nicholas F.. Fabricating a semiconductor device using precursor CMOS semiconductor substrate of a given configuration. USP1999025874327.
  78. Chang Tzong-Sheng,TWX ; Chou Chen-Cheng,TWX. Fabrication process for MOSFET devices and a reproducible capacitor structure. USP1999126004841.
  79. Korman Charles Steven. Fet array for operation at different power levels. USP1999095959357.
  80. Saran, Mukul; Martin, Charles A.; Cox, Ronald H.. Fine pitch system and method for reinforcing bond pads in semiconductor devices. USP2004116818540.
  81. Longcor Steven W.. Flash memory array having well contact structures. USP1999105973374.
  82. Saia Richard Joseph ; Durocher Kevin Matthew ; Cole Herbert Stanley. Flexible interconnect film including resistor and capacitor layers. USP1999025874770.
  83. Liang Mike. Flip chip bump distribution on die. USP1999095952726.
  84. Shenoy Jayarama N. ; Findley Paul. Flip chip circuit arrangement with redistribution layer that minimizes crosstalk. USP1999115994766.
  85. Fulcher Edwin (Palo Alto CA). Flip chip package with reduced number of package layers. USP1997115686764.
  86. Takada Norimasa (Tokyo JPX). Flip chip type semiconductor device. USP1991095046161.
  87. Lu, Hsueh-Chung Shelton; Chang, Kenny; Huang, Jimmy. Flip-chip bump arrangement for decreasing impedance. USP2004016680544.
  88. Okada Takashi,JPX ; Hirano Naohiko,JPX ; Tazawa Hiroshi,JPX ; Hosomi Eiichi,JPX ; Takubo Chiaki,JPX ; Doi Kazuhide,JPX ; Hiruta Yoichi,JPX ; Shibasaki Koji,JPX. Flip-chip connection type semiconductor integrated circuit device. USP2000086111317.
  89. Hsu, Chi-Hsing. Flip-chip die and flip-chip package substrate. USP2005036861740.
  90. Adrian Ng Choon Seng (Singapore SGX). Formation of a metal via structure from a composite metal layer. USP1997085654216.
  91. Ng Choon Seng Adrian,SGX. Formation of a metal via using a raised metal plug structure. USP1998125843839.
  92. McTeer Allen. Formation of electrical contacts to conductive elements in the fabrication of semiconductor integrated circuits. USP2001076261947.
  93. Kumar Nalin (Austin TX). Forming via holes in a multilevel substrate in a single step. USP1993075227013.
  94. Schroen Walter H. ; Archer Judith S. ; Terrill Robert E.. Fully hermetic semiconductor chip, including sealed edge sides. USP2001106303977.
  95. Lane Richard H. (Hillsboro OR) Ebel Timothy M. (Aloha OR). Gold interconnect with sidewall-spacers. USP1992095145571.
  96. Kaufman John W. (Hershey PA) Root John A. (Middletown PA) Schroeder ; III James L. (Palmyra PA). Grounding shroud for surface mounted electrical connector. USP1995115470259.
  97. Wachtler, Kurt P.; Walter, David N.; Mowatt, Larry J.. HID land grid array packaged device having electrical and optical interconnects. USP2004036707124.
  98. Nomura Shinzou (Shiga JPX) Katsushima Hiroshi (Sagamihara JPX) Kawasaki Toru (Ichihara JPX) Unoki Masao (Yokohama JPX) Nakamura Masaru (Tokyo JPX). Having a protective film of a polymer having a fluorine-containing aliphatic cyclic structure. USP1992055117272.
  99. Wollesen Donald L. (Saratoga CA). High conductivity interconnection line. USP1997085659201.
  100. Toyoda Ichihiko,JPX ; Tokumitsu Tsuneo,JPX ; Nishikawa Kenjiro,JPX ; Kamogawa Kenji,JPX. High frequency masterslice monolithic integrated circuit. USP1998045739560.
  101. Lin Mou-Shiung,TWX. High performance sub-system design and assembly. USP2001016180426.
  102. Mou-Shiung Lin TW; Jin-Yuan Lee TW. High performance system-on-chip using post passivation process and glass substrates. USP2002066399997.
  103. Ewen John E. (Yorktown Heights NY) Ponnapalli Saila (Fishkill NY) Soyuer Mehmet (Yorktown Heights NY). High-Q inductors in silicon technology without expensive metalization. USP1995085446311.
  104. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA). High-density, multi-level interconnects, flex circuits, and tape for TAB. USP1990124980034.
  105. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA). High-density, multi-level interconnects, flex circuits, and tape for tab. USP1992045106461.
  106. Losavio Aldo (Bergamo ITX) Bacchetta Maurizio (Cologno Monzese ITX). Highly-planar interlayer dielectric thin films in integrated circuits. USP1997015598028.
  107. Moura Eduardo J. ; Gronski Jan Maksymilian ; Packer Robert L. ; Luxenberg Robert A. ; Enns Frederick. Hybrid access system with AGC control of upstream channel transmit power. USP1999095959997.
  108. Zhao Bin ; Brongo Maureen R.. IC interconnect structures and methods for making same. USP2001066245663.
  109. Mou-Shiung Lin TW. Inductor structure for high performance system-on-chip using post passivation process. USP2002096455885.
  110. Forbes Leonard ; Ahn Kie Y.. Inductor with magnetic material layers. USP2001026191468.
  111. Cronin John Edward. Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same. USP1998105818110.
  112. Kloen Hendrik K.,NLX ; Huiskamp Lodewijk P.,NLX. Integrated circuit device. USP2001056229221.
  113. Nakanishi Keiichirou (Kokubunji JPX) Yamada Minoru (Hanno JPX) Saitoh Tatsuya (Kokubunji JPX) Yamamoto Kazumichi (Kokubunji JPX). Integrated circuit device having an ic chip mounted on the wiring substrate and having suitable mutual connections betwe. USP1993055212403.
  114. Lamson Michael A. (Van Alstyne TX) Edwards Darvin R. (Dallas TX). Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof. USP1992015083187.
  115. Harvey Ian. Integrated circuit device interconnection techniques. USP2001016174803.
  116. Williams Richard K. ; Kasem Mohammad. Integrated circuit die having thick bus to reduce distributed resistance. USP1999085945709.
  117. Kossives Dean P. ; Lotfi Ashraf W. ; Schneemeyer Lynn F. ; Steigerwald Michael L. ; Van Dover R. Bruce. Integrated circuit having a micromagnetic device including a ferromagnetic core and method of manufacture therefor. USP2001076255714.
  118. Shimizu Atsushi (Ome JPX) Isomura Satoru (Ome MA JPX) Yamada Takeo (Boston MA) Kobayashi Tohru (Iruma JPX) Fujimura Yoshuhiro (Ome JPX) Ito Yuko (Ome JPX). Integrated circuit having alternate rows of logic cells and I/O cells. USP1994085341049.
  119. Staudinger Joseph (Gilbert AZ) Seely Warren L. (Chandler AZ) Patterson Howard W. (Phoenix AZ). Integrated circuit having passive circuit elements. USP1995055416356.
  120. Adamic ; Jr. Fred W.. Integrated circuit including inverted dielectric isolation. USP2000076084284.
  121. Burghartz Joachim Norbert ; Edelstein Daniel Charles ; Jahnes Christopher Vincent ; Uzoh Cyprian Emeka. Integrated circuit inductor. USP1999035884990.
  122. Havemann Robert H. ; Jain Manoj K.. Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide. USP2001086278174.
  123. Chiang Ping-Wang (Los Gatos CA). Integrated circuit multilevel interconnect system and method. USP1986034576900.
  124. Imai Ryuji (Aichi JPX) Kanbe Rokuro (Aichi JPX). Integrated circuit package having a multilayered wiring portion formed on an insulating substrate. USP1995115468997.
  125. Gregoire Francois ; Madurawe Raminda ; Thalapaneni Guru. Integrated circuit pad structures. USP1999085939790.
  126. Efland, Taylor R.; Abbott, Donald C.; Bucksch, Walter; Corsi, Marco; Shen, Chi-Cheong; Erdeljac, John P.; Hutter, Louis N.; Mai, Quang X.; Wagensohner, Konrad; Williams, Charles E.; Buschbom, Milton . Integrated circuit with bonding layer over active circuitry. USP2004016683380.
  127. Shen Chi-Cheong ; Abbott Donald C. ; Bucksch Walter,DEX ; Corsi Marco ; Efland Taylor Rice ; Erdeljac John P. ; Hutter Louis Nicholas ; Mai Quang ; Wagensohner Konrad,DEX ; Williams Charles Edward. Integrated circuit with bonding layer over active circuitry. USP2000116144100.
  128. Farrar Paul A.. Integrated circuit with oxidation-resistant polymeric layer. USP2001096288442.
  129. Darko Piscevic DE. Integrated electrical circuit with passivation layer. USP2002056395454.
  130. Vigna, Benedetto; Ravanelli, Enrico Maria Alfonso. Integrated electronic device comprising a mechanical stress protection structure. USP2003086605873.
  131. Marum Steven E. (Sherman TX). Integrated injection logic electronic system with voltage regulator for multiplexed liquid crystal display. USP1980024189909.
  132. Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT). Integrated memory cube, structure and fabrication. USP1996105563086.
  133. Yasuda Mitsuru,JPX ; Sugiyama Hiroyuki,JPX ; Ito Noriyuki,JPX ; Yamashita Ryoichi,JPX ; Konno Tadashi,JPX ; Abe Yasunori,JPX ; Bizen Naomi,JPX ; Maruyama Terunobu,JPX ; Kato Yoshiyuki,JPX ; Isomura T. Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit. USP2001056240541.
  134. Stolmeijer Andre. Interconnect scheme for integrated circuits. USP1998115834845.
  135. Aoi Nobuo,JPX. Interconnect structure and method for forming the same. USP2001066242339.
  136. McTeer,Allen. Interconnect structure for use in an integrated circuit. USP2006067061111.
  137. Ahmad Umar M. U. (Both of Hopewell Junction NY) Kumar Ananda H. (Both of Hopewell Junction NY) Perfecto Eric D. (Wappingers Falls NY) Prasad Chandrika (Wappingers Falls NY) Purushothaman Sampath (Yor. Interconnect structure having improved metallization. USP1995075436412.
  138. Simpson Cindy Reidsema. Interconnect structure in a semiconductor device and method of formation. USP2001036197688.
  139. Colgan Evan George ; Rodbell Kenneth Parker ; Totta Paul Anthony ; White James Francis. Interconnect structure using Al.sub.2 -Cu for an integrated circuit chip. USP1999075925933.
  140. Chiang Chien ; Pan Chuanbin ; Ochoa Vicky M. ; Fang Sychyi ; Fraser David B. ; Sum Joyce C. ; Ray Gary William ; Theil Jeremy A.. Interconnect structure with hard mask and low dielectric constant materials. USP1999035886410.
  141. Uzodinma Okoroanyanwu ; Ramkumar Subramanian. Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques. USP2002116475904.
  142. Dubin, Valery M.; Cheng, Chin-Chang; Hussein, Makarem; Nguyen, Phi L.; Brain, Ruth A.. Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs. USP2005106958547.
  143. Frye Robert C. (Piscataway NJ) Tai King L. (Berkeley Heights NJ). Interconnection lines for wafer-scale-integrated assemblies. USP1987104703288.
  144. Sarkary ; Homi G.. Interconnection of integrated circuit metallization. USP1978084109275.
  145. David V. Horak ; William A. Klaasen ; Thomas L. McDevitt ; Mark P. Murray ; Anthony K. Stamper. Interconnection structure and method for fabricating same. USP2002086436814.
  146. Lou Chine-Gie,TWX ; Lee Horng-Ming,TWX. Interlayer dielectric planarization process. USP2001026184159.
  147. Hernandez Jorge M. (Mesa AZ) Hyslop Michael S. (Chandler AZ). Internally decoupled integrated circuit package. USP1992035095402.
  148. Zommer Nathan. Isolated multi-chip devices. USP2000086107674.
  149. Huang Richard J. (Milpitas CA) Cheung Robin W. (Cupertino CA) Rakkhit Rajat (Milpitas CA) Lee Raymond T. (Sunnyvale CA). Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC applicati. USP1997085654589.
  150. Richman Paul (St. James NY). Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer. USP1980064208780.
  151. Williams Richard K. ; Kasem Mohammad. Laternal power mosfet having metal strap layer to reduce distributed resistance. USP1998065767546.
  152. Vernon Kenneth O. (2001 Stanwood Drive Santa Barbara CA 93103). Line releasing clamp. USP1977064028780.
  153. Jeng Shin-Puu ; Taylor Kelly J.. Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials. USP1998105818111.
  154. Wollesen Donald L.. Low capacitance interconnection. USP2000116146985.
  155. Wollesen Donald L.. Low capacitance interconnection. USP1999055900668.
  156. Yegnashankaran Visvamohan ; Lin Hengyang James ; Weaver Kevin. Low capacitance multilevel metal interconnect structure and method of manufacture. USP2000086100590.
  157. Novak, W. Thomas. Low distortion kinematic reticle support. USP2004046717159.
  158. Matsuzaki Kazuo (Kanagawa JPX). Magnetic induction coil for semiconductor devices. USP1996055519582.
  159. Nakahara Moriya (Yokohama JPX) Saito Yasuyuki (Yokohama JPX) Shirai Kenichi (Yokohama JPX) Itabashi Yasushi (Tokyo JPX) Turugai Takashi (Kitagami JPX). Manufacturing a wiring formed inside a semiconductor device. USP1992055110762.
  160. Mehta, Sunil. Manufacturing process for borderless vias with respect to underlying metal. USP2003066577007.
  161. Warren M. Farnworth. Mask repattern process. USP2002076426562.
  162. Yu, Chen-Hua; Liu, Chung-Shi. Metal bond pad for low-k inter metal dielectric. USP2004036703286.
  163. Weigand Peter,DEX ; Tobben Dirk. Metalization system having an enhanced thermal conductivity. USP2000046046503.
  164. Brown Vernon L. ; Magera Yaroslaw A.. Metallization and termination process for an integrated circuit chip. USP1998085792594.
  165. Erdeljac John P. ; Hutter Louis Nicholas ; Khatibzadeh M. Ali ; Arch John Kenneth. Metallization outside protective overcoat for improved capacitors and inductors. USP2001056236101.
  166. Sharma Ravinder K. (Mesa AZ) Geyer Harry J. (Phoenix AZ) Mitchell Douglas G. (Tempe AZ). Metallization scheme providing adhesion and barrier properties. USP1990054927505.
  167. Harvey Ian Robert ; Lin Xi-Wei. Metallization technique for gate electrodes and local interconnects. USP2001036207543.
  168. Cheung Robin W. ; Ting Chiu H.. Metallized interconnection structure and method of making the same. USP2000116153521.
  169. Iacoponi, John A.. Method and apparatus for forming an under bump metallurgy layer. USP2003116649533.
  170. Tomasi Peter A. ; Zhao Tong ; St. Angel Lindo ; Schellinger Michael J. ; Nguyen Dien N. ; Bradley Wayne H.. Method and apparatus for reducing current consumption. USP2001126330234.
  171. Walker William R. (Rochester MI) Lukowski George W. (Bloomfield Hills MI). Method and apparatus for stamping weld adapters. USP1991055016461.
  172. Mistry Addi Burjorji ; Sarihan Vijay ; Kleffner James H. ; Carney George F.. Method and apparatus for stress relief in solder bump formation on a semiconductor device. USP2000066077726.
  173. Chine-Gie Lou TW. Method and structure for a conductive and a dielectric layer. USP2002066399482.
  174. Liou Ping,TWX. Method and structure of manufacturing a high-Q inductor with an air trench. USP2001126326673.
  175. Bojkov, Christo P.; Arbuthnot, Diane L.; Kunesh, Robert F.. Method for chemical etch control of noble metals in the presence of less noble metals. USP2005126979647.
  176. Gehman ; Jr. John B. (Scottsdale AZ) O\Connell Richard P. (Scottsdale AZ). Method for connection of signals to an integrated circuit. USP1996035501006.
  177. Malladi Deviprasad (Campbell CA) Ansari Shahid S. (Milpitas CA) Bogatin Eric (San Jose CA). Method for direct attachment of an on-chip bypass capacitor in an integrated circuit. USP1997055629240.
  178. Jun Young K. (Seoul KRX). Method for fabricating a semiconductor device. USP1995065427982.
  179. Yamada Yoshiaki,JPX. Method for fabricating a semiconductor device having a refractory metal pillar for electrical connection. USP1999065910020.
  180. Wojnarowski Robert John ; Rose James Wilson ; Balch Ernest Wayne ; Douglas Leonard Richard ; Downey Evan Taylor ; Gdula Michael. Method for fabricating a thin film inductor. USP2000036040226.
  181. Yamazaki Shunpei,JPX ; Takemura Yasuhiko,JPX ; Mase Akira,JPX ; Uochi Hideki,JPX. Method for fabricating a thin film semiconductor device. USP1999126004831.
  182. Sundaram Lalgudi M. G. (Scottsdale AZ) Tracht Neil (Mesa AZ). Method for fabricating a vertical trench inductor. USP1994125372967.
  183. Chen Lai-Juh,TWX ; Wang Chien-Mei,TWX. Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant pol. USP1999015858869.
  184. Tsai Lih-Shyng (Hsin-Chu TWX) Lin Jiunn-Jyi (Hsin-Chu TWX) Lin Kwang-Ming (Hsin-Chu TWX) Ying Shu-Lan (Pan-Chiau TWX). Method for field inversion free multiple layer metallurgy VLSI processing. USP1993105252515.
  185. Wakabayashi Takeshi (Hidaka JPX) Suzuki Akira (Musashino JPX) Yokoyama Shigeru (Chofu JPX). Method for forming a bump electrode for a semiconductor device. USP1992045108950.
  186. Boyd Melissa D. (Corvallis OR). Method for forming a conductive pattern on an integrated circuit. USP1993075226232.
  187. Braeckelmann Gregor ; Venkatraman Ramnath ; Herrick Matthew Thomas ; Simpson Cindy R. ; Fiordalice Robert W. ; Denning Dean J. ; Jain Ajay ; Capasso Cristiano. Method for forming a semiconductor device. USP2001046218302.
  188. Mehta Sunil D. ; Li Xiao-Yu. Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect. USP2001076261944.
  189. Lee Jia-Sheng,TWX. Method for forming a thin-film resistor. USP2001086272736.
  190. Elenius Peter ; Hollack Harry. Method for forming chip scale package. USP2001096287893.
  191. Singh Abha R. ; Balasinski Artur P. ; Li Ming M.. Method for forming controlled voids in interlevel dielectric. USP1998125847464.
  192. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC). Method for forming dense multilevel interconnection metallurgy for semiconductor devices. USP1984014423547.
  193. Lin Mou-Shiung,TWX. Method for forming high performance system-on-chip using post passivation process. USP2001106303423.
  194. Yoo Chue-San,TWX ; Lee Jin-Yuan,TWX. Method for forming vias in multi-level integrated circuits, for use with multi-level metallizations. USP1999015861673.
  195. Leu, Jihperng; Wu, Chih-I; Zhou, Ying; Kloster, Grant M.. Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics. USP2003086605549.
  196. Cole ; Jr. Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Rexford NY). Method for making an electronics module having air bridge protection without large area ablation. USP1996085548099.
  197. Farrar Paul A. ; Forbes Leonard. Method for making high-Q inductive elements. USP2000026025261.
  198. Frye Robert C. (Piscataway NJ) Tai King L. (Berkeley Heights NJ). Method for making multichip circuits using active semiconductor substrates. USP1996075534465.
  199. DeHaven Robert Keith (Austin TX) Wenzel James F. (Austin TX). Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located. USP1997125701666.
  200. Gansauge Peter (Boeblingen DEX) Kreuter Volker (Schoenaich DEX) Schettler Helmut (Dettenhausen DEX). Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer. USP1993095244833.
  201. Matsuki Hirohisa,JPX ; Kado Kenichi,JPX ; Watanabe Eiji,JPX ; Imamura Kazuyuki,JPX ; Yurino Takahiro,JPX. Method for manufacturing semiconductor device with pad structure. USP2001056232147.
  202. Matumoto Akira,JPX. Method for manufacturing semiconductor devices having dual damascene structure. USP2000126165899.
  203. Cadet, Bernard. Method for marking integrated circuits with a laser. USP2003056559409.
  204. Hendel Rudi (26 Ridge Rd. Summit NJ 07901) Levinstein Hyman (132 Robbins Ave. Berkeley Heights NJ 07974). Method for planarization of submicron vias and the manufacture of semiconductor integrated circuits. USP1994115360524.
  205. Carlos J. Sambucetti ; Daniel C. Edelstein ; John G. Gaudiello ; Judith M. Rubino ; George Walker. Method for preparing a conductive pad for electrical connection and conductive pad formed. USP2002016335104.
  206. Wu Kun-Lin,TWX ; Lu Horng-Bor,TWX. Method for preventing poisoned vias and trenches. USP2000066071806.
  207. Koblinger Otto (Korntal-Munchingen DEX) Trumpp Hans-Joachim (Filderstadt DEX). Method for producing an integrated circuit structure with a dense multilayer metallization pattern. USP1992045109267.
  208. Agarwala Birendra N. ; Dalal Hormazdyar M. ; Nguyen Du B. ; Rathore Hazara S.. Method for providing electrically fusible links in copper interconnection. USP2000036033939.
  209. Zhu Min,SGX ; Shao Kai,SGX ; Chu Shao-Fu Sanford,SGX. Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions. USP2000106133079.
  210. Leung Pak K.,CAX ; Emesh Ismail T.,CAX. Method of adding on chip capacitors to an integrated circuit. USP1998085789303.
  211. Gaul Stephen Joseph (Melbourne FL). Method of bonding wafers having vias including conductive material. USP1997075646067.
  212. Chang Mark S. (Los Altos CA) Cheung Robin W. (Cupertino CA). Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed perfo. USP1996095559055.
  213. Robl, Werner; Goebel, Thomas; Brintzinger, Axel Christoph; Friese, Gerald. Method of eliminating back-end rerouting in ball grid array packaging. USP2004046720212.
  214. Ilderem Vida (Puyallup WA) Iranmanesh Ali A. (Federal Way WA) Solheim Alan G. (Puyallup WA) Blair Christopher S. (Puyallup WA) Jerome Rick C. (Puyallup WA) Lahri Rajeeva (Puyallup WA) Biswal Madan (P. Method of fabricating BiCMOS device. USP1994085338696.
  215. Tehrani Saied N. ; Chen Eugene ; Durlam Mark ; Zhu Xiaodong T. ; Tracy Clarence J.. Method of fabricating GMR devices. USP1999015861328.
  216. Gardner Donald S.. Method of fabricating a barrier against metal diffusion. USP1998075783483.
  217. F. Scott Johnson. Method of fabricating a miniaturized integrated circuit inductor and transformer fabrication. USP2002086441715.
  218. Yamaguchi, Yoshihide; Tenmei, Hiroyuki; Hozoji, Hiroshi; Kanda, Naoya. Method of fabricating a wafer level chip size package utilizing a maskless exposure. USP2004086780748.
  219. Benjamin N. Eldridge ; Gary W. Grube ; Igor Y. Khandros ; Gaetan L. Mathieu. Method of fabricating an interconnection element. USP2002016336269.
  220. Sakamoto, Tatsuya. Method of fabricating semiconductor device. USP2004036709973.
  221. Geffken Robert M. ; Luce Stephen E.. Method of forming a self-aligned copper diffusion barrier in vias. USP1999115985762.
  222. Wetzel Jeffrey T. ; Stankus John J.. Method of forming a semiconductor device having dual inlaid structure. USP1999075920790.
  223. Alford Ronald C. ; Stengel Robert E. ; Weisman Douglas H. ; Marlin George W.. Method of forming a three-dimensional integrated inductor. USP1999126008102.
  224. Hanazono Masanobu (Hitachi JA) Asai Osamu (Hitachi JA) Tamura Katsumi (Hitachi JA). Method of forming deposition films for use in multi-layer metallization. USP1977054024041.
  225. Wang Fei ; Cheng Jerry. Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer. USP2001056235628.
  226. Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A.. Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect. USP2000026025275.
  227. Mario Napolitano IT. Method of forming interconnectings in semiconductor devices. USP2002116475898.
  228. Lee Jin-Yuan,TWX ; Wang Chen-Jong,TWX. Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures. USP2001076265301.
  229. Feldner Klaus,DEX ; Grewal Virinder,DEX ; Vollmer Bernd ; Schnabel Rainer Florian. Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide. USP2001106300235.
  230. Buynoski Matthew S. ; Lin Ming-Ren. Method of forming multiple levels of patterned metallization. USP2001036207553.
  231. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown. Method of forming semiconductor device including interconnect barrier layers. USP2004036713381.
  232. Akram, Salman. Method of improving copper interconnects of semiconductor devices for bonding. USP2003046544880.
  233. Bahrle Dieter (Schoenaich DEX) Frasch Peter (Boeblingen DEX) Konig Wilfried (Gaertringen DEX) Schwerdt Friedrich (Sindelfingen DEX) Thelen Ursula (Sindelfingen DEX) Vogtmann Theodor (Holzgerlingen DE. Method of improving the adherence of metallic conductive lines on polyimide layers. USP1979054152195.
  234. Kanehachi Kaoru (Tokyo JPX). Method of making a combined semiconductor device and inductor. USP1995015384274.
  235. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M.. Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer. USP2000086100184.
  236. Naoteru Matsubara JP; Hideki Mizuhara JP. Method of making a dual damascene structure with modified insulation. USP2002066399478.
  237. Chang Kenneth (Hopewell Junction NY) Czornyj George (Poughkeepsie NY) Farooq Mukta S. (Hopewell Junction NY) Kumar Ananda H. (Hopewell Junction NY) Pitler Marvin S. (late of Poughkeepsie NY by Peter . Method of making a multilayer thin film structure. USP1993115266446.
  238. Pomante, Louis N.. Method of making a semiconductor device with a seal. USP1983044380115.
  239. Dow Stephen (Chandler AZ) Maass Eric C. (Scottsdale AZ) Marlin Bill (Phoenix AZ). Method of making an electronic device having an integrated inductor. USP1995125478773.
  240. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S.. Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines. USP1998105827776.
  241. Givens John H.. Method of making an interconnect structure. USP2000056060385.
  242. Reisman Arnold (Raleigh NC) Turlik Iwona (Raleigh NC). Method of making high density semiconductor structure. USP1992125168078.
  243. Anatoly Feygenson ; Dean P. Kossives ; Ashraf W. Lotfi ; Lynn F. Schneemeyer ; Michael L. Steigerwald ; R. Bruce Van Dover. Method of making integrated circuit having a micromagnetic device. USP2002086440750.
  244. Chu Shau-Fu Sanford,SGX ; Chew Kok Wai Johnny,SGX ; Chua Chee Tee,SGX ; Cha Cher Liang,SGX. Method of making spiral-type RF inductors having a high quality factor (Q). USP2000106140197.
  245. Chikawa Yasunori (Nara JPX) Sasaki Shigeyuki (Nara JPX) Mori Katsunobu (Nara JPX) Maeda Takamichi (Nara JPX) Hayakawa Masao (Kyoto JPX). Method of manufacturing a bump electrode. USP1994055310699.
  246. Tokushige, Ryoji; Takai, Nobuyuki; Shinogi, Hiroyuki; Ono, Seiichi. Method of manufacturing a semiconductor device. USP2003046555459.
  247. Yamada Yoshiaki,JPX. Method of manufacturing a semiconductor device using a silicon fluoride oxide film. USP1998105827778.
  248. Peters Johannes S. (Nijmegen NLX). Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided o. USP1988124789647.
  249. Brandli Gerold (Aarau CHX) Bachmann Guido (Sempach CHX). Method of manufacturing multi-layer thin film circuits containing integrated thin film resistors. USP1993075227012.
  250. Tsuboi Atsushi,JPX. Method of manufacturing semiconductor device having multilevel interconnection. USP1998035726098.
  251. Naik Mehul ; Broydo Samuel. Method of producing an interconnect structure for an integrated circuit. USP2001066245662.
  252. Ito Daisuke,JPX ; Kitahara Yuichi,JPX. Method of producing semiconductor device comprising insulation layer having improved resistance and semiconductor device produced thereby. USP2001036200888.
  253. Ho Paul Kwok Keung,SGX ; Zhou Mei Sheng,SGX ; Gupta Subhash,SGX. Method to create a controllable and reproducible dual copper damascene structure. USP2001026184138.
  254. Shih, Tsu. Method to eliminate via poison effect. USP2004116821896.
  255. Tsai Chao-Chieh,TWX. Method to fabricate high Q inductor by redistribution layer when flip-chip package is employed. USP2001016180445.
  256. Smoak, Richard C.. Method to improve the reliability of thermosonic gold to aluminum wire bonds. USP2003076593222.
  257. Chan Lap ; Chew Johnny Kok Wai,SGX ; Cha Cher Liang,SGX ; Chua Chee Tee,SGX. Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology. USP2001046221727.
  258. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy. Method/structure for creating aluminum wirebound pad on copper BEOL. USP2001026187680.
  259. Kie Y. Ahn ; Leonard Forbes. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals. USP2002086429120.
  260. Osann ; Jr. Robert ; Eltoukhy Shafy. Methods and apparatuses for binning partially completed integrated circuits based upon test results. USP2000106133582.
  261. Xia Li-Qun ; Yieh Ellie ; Nemani Srinivas. Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions. USP1999105963840.
  262. Lien Chuen-Der. Methods for fabricating a bonding pad having improved adhesion to an underlying structure. USP1999115989991.
  263. Desaigoudar Chan M. (Los Gatos CA) Gupta Suren (San Jose CA). Methods for fabrication of thin film inductors, inductor networks and integration with other passive and active devices. USP1994125370766.
  264. Wu Zhiqiang ; Jiang Tongbi ; Akram Salman. Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly. USP2001066245594.
  265. Zhao Bin. Methods for forming high-performing dual-damascene interconnect structures. USP2000066071809.
  266. Zhao Ji ; Teng Chih Sieh. Methods for making VLSI capacitors and high Q VLSI inductors using metal-filled via plugs. USP2000116146958.
  267. Ahn,Kie Y.; Forbes,Leonard. Methods for making copper and other metal interconnections in integrated circuits. USP2006016984891.
  268. Valery Dubin. Methods for making interconnects and diffusion barriers in integrated circuits. USP2002036359328.
  269. Marcinkiewicz Walter M.. Methods for packaging integrated circuit devices including cavities adjacent active regions. USP1999126001673.
  270. Cronin John Edward (Milton VT) Howell Wayne John (Williston VT) Kalter Howard Leo (Colchester VT) Marmillion Patricia Ellen (Colchester VT) Palagonia Anthony (Underhill VT) Pierson Bernadette Ann (So. Methods for precise definition of integrated circuit chip edges. USP1997115691248.
  271. Lin, Mou-Shiung; Ting, Tah-Kang Joseph. Methods of IC rerouting option for multiple package system applications. USP2003076593649.
  272. Averkiou George ; Trask Philip A.. Methods of fabricating an HDMI decal chip scale package. USP1998105817541.
  273. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA). Methods of forming an interconnect on a semiconductor substrate. USP1997035612254.
  274. Donado Rafael A. (Chicago IL) Ong Estela T. (Chicago IL). Methods of making anodes for high temperature fuel cells. USP1993075229221.
  275. Kim, Sarah E.; Lee, Kevin J.; George, Anna M.. Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow. USP2005096943440.
  276. Jean-Michel Karam FR; Laurent Basteres FR; Ahmed Mhani FR; Catherine Charrier FR; Eric Bouchon FR; Guy Imbert FR; Patrick Martin FR; Fran.cedilla.ois Valentin FR. Microcomponents of the microinductor or microtransformer type and process for fabricating such microcomponents. USP2002086429764.
  277. Stratton, Thomas G.; Gardner, Gary R.; Rahn, Curtis H.. Microelectromechanical device with integrated conductive shield. USP2005106952042.
  278. Licari James J. (Whittier CA) Smith Deborah J. (Fountain Valley CA). Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers. USP1996015485038.
  279. Naoko Ono JP; Yuji Iseki JP; Keiichi Yamaguchi JP; Junko Onomura JP; Eiji Takagi JP. Microwave semiconductor device having coplanar waveguide and micro-strip line. USP2002096455880.
  280. Nguyen Chanh N. ; Nguyen Nguyen Xuan ; Le Minh V.. Modulation-doped field-effect transistors and fabrication processes. USP2000086100548.
  281. Jacobs Scott L. (Peekskill NY) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Peekskill NY) Schnurmann Henri D. (Monsey NY) Zingher Arthur R. (White Plains NY). Module for packaging semiconductor integrated circuit chips on a base substrate. USP1989094866507.
  282. Costa Julio C. (Phoenix AZ) Burger Wayne R. (Phoenix AZ) Camilleri Natalino (Tempe AZ) Dragon Christopher P. (Tempe AZ) Lamey Daniel J. (Phoenix AZ) Lovelace David K. (Chandler AZ) Ngo David Q. (Phoe. Monolithic high frequency integrated circuit structure having a grounded source configuration. USP1996115578860.
  283. Laurent Basteres FR; Ahmed Mhani FR; Fran.cedilla.ois Valentin FR; Jean-Michel Karam FR. Monolithic integrated circuit incorporating an inductive component and process for fabricating such an integrated circuit. USP2002106459135.
  284. Abidi Asad A. (Los Angeles CA) Chang James Y.-C. (Los Angeles CA). Monolithic passive component. USP1996075539241.
  285. Jin Sang-Hun,KRX. Mounting coordinate input method and apparatus for surface mount device. USP2000056064758.
  286. Bissey Lucien J.. Multi-capacitance lead frame decoupling device. USP2001026184574.
  287. Massingill, Thomas J.; McCormack, Mark Thomas; Wang, Wen-Chou Vincent. Multi-chip module and method for forming and method for deplating defective capacitors. USP2005046882045.
  288. Oda, Noriaki. Multi-layer interconnection structure in semiconductor device and method for fabricating same. USP2003036531779.
  289. Yano Kousaku,JPX ; Ueda Tetsuya,JPX. Multi-layer wiring structure having varying-sized cutouts. USP1998065760429.
  290. Ping Liou TW. Multi-level spiral inductor structure having high inductance (L) and high quality factor (Q). USP2002076420773.
  291. Shue Shau-Lin,TWX ; Tsai Ming-Hsing,TWX ; Tsai Wen-Jye,TWX ; Yu Chen-Hua,TWX. Multi-step electrochemical copper deposition process with improved filling capability. USP2000106140241.
  292. Liu Yowjuang William. Multilayer floating gate field effect transistor structure for use in integrated circuit devices. USP1999035889302.
  293. Mototsugu Okushima JP. Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor. USP2002026346471.
  294. Choudhury Ratan K. ; Kapoor Ashok K. ; Menon Satish. Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection. USP1998085789783.
  295. Cole ; Jr. Herbert S. (Scotia NY) Rose James W. (Delmar NY) Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY). Mutliple lamination high density interconnect process and structure employing thermoplastic adhesives having sequentiall. USP1992105157589.
  296. Worley Eugene Robert ; Mann Richard Arthur. Optional on chip power supply bypass capacitor. USP2000116147857.
  297. Hsuan Min-Chih,TWX ; Liou Fu-Tai,TWX. Package-free bonding pad structure. USP2000026031293.
  298. Degani Yinon (Highland Park NJ) Dudderar Thomas D. (Chatham NJ) Han Byung J. (Scotch Plains NJ) Lyons Alan M. (New Providence NJ) Tai King L. (Berkeley Heights NJ). Packaging multi-chip modules without wire-bond interconnection. USP1997035608262.
  299. Cronin John E. (Milton) Farrar ; Sr. Paul A. (South Burlington) Linde Harold G. (Richmond) Previti-Kelly Rosemary A. (Richmond VT). Passivation of metal in metal/polyimide structure. USP1993035194928.
  300. Bohr, Mark T.. Passivation structure for an integrated circuit. USP2003056566737.
  301. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R.. Personalization structure for semiconductor devices. USP1999035883435.
  302. Smith Donald L. ; Thornton Robert L. ; Chua Christopher L. ; Fork David K.. Photolithographically patterned spring contact and apparatus and methods for electrically contacting devices. USP1999085944537.
  303. Tung, Francisca. Pillar connections for semiconductor chips and method of manufacture. USP2003066578754.
  304. Seshan Krishna ; Mielke Neal R.. Planar guard ring. USP2000106137155.
  305. Wu Andrew L. (Shrewsbury MA). Planar interconnect for integrated circuits. USP1986104617193.
  306. Lou Chine-Gie,TWX. Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits. USP1998065759906.
  307. Chia-Shiun Tsai TW; Chao-Cheng Chen TW; Hun-Jan Tao TW. Plasma etch method for forming patterned oxygen containing plasma etchable layer. USP2002086440863.
  308. Ting Chiu ; Dubin Valery. Plated copper interconnect structure. USP1999105969422.
  309. Jao Kuo-Hao,TWX ; Chen Yung-Shun,TWX. Poly-load resistor for SRAM cell. USP1999035885862.
  310. Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Howell Wayne J. (South Burlington VT) Miller Christopher P. (Underhill VT) Perlman David J. (Wappingers Falls NY). Polyimide-insulated cube package of stacked semiconductor device chips. USP1995125478781.
  311. Mastrangelo Carlos H. ; Man Piu F. ; Webster James R.. Polymer-based micromachining for microfluidic devices. USP2000106136212.
  312. Lee Virgil J. (La Verne CA). Polyquinazolines and methods for their preparation. USP1997115686560.
  313. Tseng Horng-Huei (Hsin Chu TWX). Polysilicon contact stud process. USP1996125587338.
  314. Mou-Shiung Lin TW; Jin-Yuan Lee TW. Post passivation interconnection schemes on top of the IC chips. USP2002126495442.
  315. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng. Post passivation metal scheme for high-performance integrated circuit devices. USP2003116649509.
  316. Chen Chao-Cheng,TWX. Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesqu. USP1999105970376.
  317. Fukuyama Shun-ichi (Atsugi JPX) Yoneda Yasuhiro (Machida JPX) Miyagawa Masashi (Isehara JPX) Nishii Kota (Isehara JPX) Matsuura Azuma (Atsugi JPX). Preparation of lower alkyl polysilsesquioxane and formation of insulating layer of silylated polymer on electronic circu. USP1991014988514.
  318. E. Henry Stevens. Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece. USP2002046376374.
  319. Rao Raman K. (Palo Alto CA). Process enhancement using molybdenum plugs in fabricating integrated circuits. USP1990124975386.
  320. Lin Yung-Fa,TWX. Process for creating vias using pillar technology. USP1999075929525.
  321. Nanda Madan M. (Reston VA) Peterman Steven L. (Manassas VA) Stanasolovich David (Manassas VA). Process for defining vias through silicon nitride and polyimide. USP1990124978419.
  322. Vivian W. Ryan. Process for fabricating copper interconnect for ULSI integrated circuits. USP2002066410435.
  323. Misawa Nobuhiro (Kawasaki JPX). Process for fabricating integrated circuit devices. USP1995115470789.
  324. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT). Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit. USP1990104962058.
  325. Hall Mark D. ; Ferguson Gregory Steven ; Mitchell Joel Patrick ; Suryanata Johanes P. D.. Process for forming a semiconductor device. USP1999095960306.
  326. Jain Ajay. Process for forming a semiconductor device. USP1998105821168.
  327. Waldo Whit G.. Process for forming a semiconductor device. USP1999075924005.
  328. Sun Shih-Wei (Austin TX) Kosa Yasunobu (Austin TX) Yeargain John R. (Austin TX). Process for forming a structure which electrically shields conductors. USP1993115262353.
  329. Flynn Todd M. ; Argento Christopher W. ; Larsen Larry J.. Process for forming an electrical device. USP2001106300234.
  330. Cronin John E. (Milton VT) Kaanta Carter W. (Colchester VT) Previti-Kelly Rosemary A. (Richmond VT) Ryan James G. (Essex Junction VT). Process for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositio. USP1992025091289.
  331. Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX. Process for making a chip sized semiconductor device. USP1999095960308.
  332. Chunlin Liang ; Larry E. Mosley ; Xiao Chun Mu. Process for making active interposer for high performance packaging applications. USP2002106461895.
  333. Bothra Subhas ; Haskell Jacob. Process for making self-aligned conductive via structures. USP2000106133635.
  334. Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN). Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal. USP1997095665639.
  335. Ikeda Osamu,JPX ; Nakamura Yoshio,JPX. Process for producing electrode for semiconductor element and semiconductor device having the electrode. USP2001046218223.
  336. Dureseti Chidambarrao ; Ronald G. Filippi ; Robert Rosenberg ; Thomas M. Shaw ; Timothy D. Sullivan ; Richard A. Wachnik. Process for producing metal interconnections and product produced thereby. USP2002076417572.
  337. Kelly Kimberley A. ; Malhotra Ashwani K. ; Perfecto Eric D. ; Yu Roy. Process for releasing a thin-film structure from a substrate. USP2000036036809.
  338. Sanders Josef (Cologne DEX) Dieterich Dieter (Leverkusen DEX). Process for the preparation of N,N-disubstituted mono- and oligourethanes. USP1992075130457.
  339. Scheifele Fredy,CHX. Process for the production of a multi-chamber packaging tube. USP2001016174393.
  340. Sachdev Krishna G. (Hopewell Junction NY) Kellner Benedikt M. J. (Wappingers Falls NY) McGuire Kathleen M. (Wallkill NY) Sorce Peter J. (Poughkeepsie NY). Process for thin film interconnect. USP1993085231751.
  341. Quinn ; Daniel J. (Carrollton TX) Mulholland Wayne A. (Plano TX) Bond Robert H. (Carrollton TX) Olla Michael A. (Flower Mound TX) Cupples Jerry S. (Carrollton TX) Tsitovsky Ilya L. (Farmers Branch TX. Process of forming integrated circuits with contact pads in a standard array. USP1987084685998.
  342. Chang Sung Chul ; Khandros Igor Y. ; Smith William D.. Process of mounting spring contacts to semiconductor devices. USP2001016168974.
  343. Stephen L. Skala ; Subhas Bothra. Programmable integrated circuit structures and methods for making the same. USP2002036355969.
  344. Dangelo Carlos (Los Gatos CA). Programmable microsystems in silicon. USP1997095665989.
  345. Subhas Bothra. Programmable semiconductor device structures and methods for making the same. USP2002106472253.
  346. Leibovitz Jacques ; Yu Park-Kee ; Zhu Ya Yun ; Cobarruviaz Maria L. ; Swindlehurst Susan J. ; Chang Cheng-Cheng ; Scholz Kenneth D.. Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps. USP2000016011314.
  347. Anand Yoginder ; Chinoy Percy Bomi. Reduced parasitic capacitance semiconductor devices. USP1999035883422.
  348. Moore Paul McKayCTY Burlingame. Reflectance enhancing thin film stack in which pairs of dielectric layers are on a reflector and liquid crystal is on the dielectric layers. USP2000096124912.
  349. Galloway Terry R.. Removal of extended bond pads using intermetallics. USP1999035886414.
  350. Subhash Gupta SG; Mei-Sheng Zhou SG; Simon Chooi SG; Sangki Hong SG. Reversed damascene process for multiple level metal interconnects. USP2002036352917.
  351. Cole ; Jr. Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Scotia NY) Wojnarowski Robert J. (Ballston Lake NY) Lupinski John H. (Vienna VA). Reworkable high density interconnect structure incorporating a release layer. USP1995075434751.
  352. Ikeda Shuji,JPX ; Meguro Satoshi,JPX ; Hashiba Soichiro,JPX ; Kuramoto Isamu,JPX ; Koike Atsuyoshi,JPX ; Sasaki Katsuro,JPX ; Ishibashi Koichiro,JPX ; Yamanaka Toshiaki,JPX ; Hashimoto Naotaka,JPX ; . SRAM having load transistor formed above driver transistor. USP1998115834851.
  353. Liu Meng-Chang,TWX. Self-aligned connection to underlayer metal lines through unlanded via holes. USP2000016015751.
  354. Takagi Mariko,JPX. Semiconductor apparatus and manufacturing method therefor. USP2001016169019.
  355. Kumamoto, Nobuhisa; Samejima, Katsumi. Semiconductor chip and production process therefor. USP2004036707159.
  356. Yamaha Takahisa,JPX ; Inoue Yushi,JPX ; Naito Masaru,JPX. Semiconductor chip capable of supressing cracks in insulating layer. USP1998065763936.
  357. Heo Young Wook,KRX. Semiconductor chip scale package and method of producing such. USP1999065915169.
  358. Lauvray Olivier J. ; Rodriguez David. Semiconductor component comprising an electrostatic-discharge protection device. USP2000036040604.
  359. Hiatt, William M.; Farnworth, Warren M.; Watkins, Charles M.; Sinha, Nishant. Semiconductor component having encapsulated, bonded, interconnect contacts. USP2005066906418.
  360. Abercrombie David A. ; Brownson Rickey S. ; Cherniawski Michael R.. Semiconductor component with multi-level interconnect system and method of manufacture. USP1998085798568.
  361. Hajime Iizuka JP. Semiconductor device. USP2002106472745.
  362. Koyama,Jun; Ohtani,Hisashi; Ogata,Yasushi; Yamazaki,Shunpei. Semiconductor device. USP2008017323717.
  363. Tanaka, Kazuo. Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal. USP2004066756675.
  364. Nishiyama Akira,JPX. Semiconductor device and a method of manufacturing the same. USP2001036207486.
  365. Shigeru Harada JP; Takeru Matsuoka JP; Hiroki Takewaka JP. Semiconductor device and fabrication process therefor. USP2002076417575.
  366. Ito Kazunori,JPX ; Irinoda Mitsugu,JPX ; Ueno Kaichi,JPX ; Ishida Mamoru,JPX ; Kuroda Takahiko,JPX. Semiconductor device and manufacturing method for the same. USP1998125847466.
  367. Shimizu, Hironobu; Fujimoto, Koji; Horio, Masahiro. Semiconductor device and manufacturing method thereof. USP2003036538326.
  368. Kikuchi, Hidekazu. Semiconductor device and method for manufacturing. USP2003026518092.
  369. Yoshizawa Shunichi,JPX. Semiconductor device and method for manufacturing the same. USP2001096294451.
  370. Yanagida, Toshiharu. Semiconductor device and method of fabricating the same. USP2003046545355.
  371. Hashimoto Nobuaki,JPX. Semiconductor device and method of making the same, circuit board, and electronic instrument. USP2001076255737.
  372. Wada, Junichi; Sakata, Atsuko; Katata, Tomio; Usui, Takamasa; Hasunuma, Masahiko; Shibata, Hideki; Kaneko, Hisashi; Hayasaka, Nobuo; Okumura, Katsuya. Semiconductor device and method of manufacturing the same. USP2004016673704.
  373. Tongbi Jiang. Semiconductor device for attachment to a semiconductor substrate. USP2002046380626.
  374. Ahn, Hokyun; Mun, Jae Kyoung; Kim, Haecheon. Semiconductor device having T-shaped gate electrode and method of manufacturing the same. USP2005126979871.
  375. Sasaki Keiichi,JPX ; Kunishima Iwao,JPX. Semiconductor device having WNF film and method of manufacturing such a device. USP1999015861675.
  376. Aoki, Yutaki; Mihara, Ichiro; Wakabayashi, Takeshi; Watanabe, Katsumi. Semiconductor device having a barrier layer. USP2003046545354.
  377. Yong, Lois E.; Harper, Peter R.; Tran, Tu Anh; Metz, Jeffrey W.; Leal, George R.; Dinh, Dieu Van. Semiconductor device having a bond pad and method therefor. USP2005016844631.
  378. Hosomi Eiichi,JPX ; Takubo Chiaki,JPX ; Tazawa Hiroshi,JPX ; Shibasaki Koji,JPX. Semiconductor device having a bump electrode connected to an inner lead. USP1998065773888.
  379. Kim Seong Jin,KRX. Semiconductor device having a bump structure and test electrode. USP1998125854513.
  380. Aoki, Yutaka. Semiconductor device having a chip size package including a passive element. USP2003106639299.
  381. Suminoe,Shinji; Nakanishi,Hiroyuki; Ishio,Toshiya; Iwazaki,Yoshihide; Mori,Katsunobu. Semiconductor device having a leading wiring layer. USP2006087091616.
  382. Toshiaki Hasegawa JP; Hajime Nakayama JP. Semiconductor device having a low dielectric layer as an interlayer insulating layer. USP2002096452274.
  383. Irinoda Mitsugu,JPX. Semiconductor device having a minute contact hole. USP1998035726499.
  384. Aoyama Masaharu (Fujisawa JPX) Abe Masahiro (Yokohama JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Kitakyushu JPX). Semiconductor device having a multilayer wiring structure using a polyimide resin. USP1986104618878.
  385. Watatani Hirofumi,JPX. Semiconductor device having a multilayered interconnection structure. USP2000116153511.
  386. Hayashide Yoshio (Hyogo JPX). Semiconductor device having a planarized surface. USP1996035500558.
  387. Ohkura Yoshiyuki,JPX ; Harada Hideki,JPX. Semiconductor device having a porous insulation film. USP2001046218318.
  388. Harada Shigeru (Hyogo JPX) Ishimaru Kazuhiro (Hyogo JPX) Hagi Kimio (Hyogo JPX). Semiconductor device having a titanium and a titanium compound multilayer interconnection structure. USP1994085341026.
  389. Downey, Susan H.; Miller, James W.; Hall, Geoffrey B.. Semiconductor device having a wire bond pad and method therefor. USP2003096614091.
  390. Toyosawa, Kenji; Ono, Atsushi; Chikawa, Yasunori; Sakaguchi, Nobuhisa; Nakamura, Nakae; Nakata, Yukinori. Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film. USP2005036864562.
  391. Kusuyama Koichi,JPX. Semiconductor device having aluminum interconnection and method of manufacturing the same. USP1999025869901.
  392. Akahori, Takashi. Semiconductor device having an adhesion layer. USP2004046720659.
  393. Hidetoshi Koike JP. Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire. USP2002056392300.
  394. Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX. Semiconductor device having an element with circuit pattern thereon. USP1998115834844.
  395. Parrillo Louis C. (Austin TX) Klein Jeffrey L. (Austin TX). Semiconductor device having an improved metal interconnect structure. USP1995085442235.
  396. Wenzel James F. (Austin TX) Chopra Mona A. (Austin TX) Foster Stephen W. (Dripping Springs TX). Semiconductor device having built-in high frequency bypass capacitor. USP1997065635767.
  397. Sato Susumu (Tokyo JPX) Shiba Hiroshi (Tokyo JPX). Semiconductor device having bump terminal electrodes. USP1980024188636.
  398. Yamazaki Toru,JPX. Semiconductor device having inductor element made of first conductive layer of spiral configuration electrically connected to second conductive layer of insular configuration. USP1999126002161.
  399. Takamori Kazuo,JPX. Semiconductor device having long pads and short pads alternated for fine pitch without sacrifice of probing. USP1999126008542.
  400. Satonaka Koichiro (Fuchu JA). Semiconductor device having multi-layer wiring structure with additional through-hole interconnection. USP1977114060828.
  401. Hyakutake Yasuhito,JPX. Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof. USP2000076087250.
  402. Hyakutake Yasuhito,JPX. Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof. USP1998065763954.
  403. Lee Ji-Min ; Santandrea Joseph F. ; Lien Chuen-Der ; Hansen Anita ; Perham Leonard. Semiconductor device having programmable interconnect layers. USP2001046222212.
  404. Homma, Soichi; Miyata, Masahiro; Ezawa, Hirokazu. Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same. USP2004096798050.
  405. Ishii Kazutoshi (Tokyo JPX). Semiconductor device having two-layered passivation film. USP1991115065222.
  406. Matsumoto Hiroshi (Hyogo JPX). Semiconductor device in which wiring layer is formed below bonding pad. USP1991014984061.
  407. Amishiro Hiroyuki,JPX ; Igarashi Motoshige,JPX. Semiconductor device including a plurality of interconnection layers. USP2001096288447.
  408. Fujiki Noriaki (Hyogo JPX) Harada Shigeru (Hyogo JPX) Adachi Hiroshi (Hyogo JPX) Adachi Etsushi (Hyogo JPX). Semiconductor device including silicon ladder resin layer. USP1996045510653.
  409. Nozaki Masahiko (Hyogo JPX). Semiconductor device structure including multiple interconnection layers with interlayer insulating films. USP1996035502337.
  410. Kunimatsu Yasuyoshi,JPX ; Furuzawa Akira,JPX ; Sata Akifumi,JPX. Semiconductor device with a decoupling capacitor mounted thereon having a thermal expansion coefficient matched to the d. USP1998065767564.
  411. Matsuno Tadashi,JPX. Semiconductor device with improved adhesion between titanium-based metal layer and insulation film. USP2000046046502.
  412. Matsuno Tadashi,JPX. Semiconductor device with improved adhesion between titanium-based metal wiring layer and insulation film. USP1999025874779.
  413. Mametani Tomoharu,JPX ; Nagai Yukihiro,JPX. Semiconductor device with improved interconnection. USP2001016175156.
  414. Matsuki Hirohisa,JPX ; Kado Kenichi,JPX ; Watanabe Eiji,JPX ; Imamura Kazuyuki,JPX ; Yurino Takahiro,JPX. Semiconductor device with pad structure. USP1999105969424.
  415. Anzai,Noritaka. Semiconductor device with signal line having decreased characteristic impedance. USP2007077239028.
  416. Watanabe Hiroyuki,JPX ; Mizuhara Hideki,JPX ; Misawa Kaori,JPX ; Hirase Masaki,JPX ; Aoe Hiroyuki,JPX. Semiconductor devices and an insulating layer with an impurity. USP2001076268657.
  417. Morozumi, Yukio. Semiconductor devices and methods for manufacturing the same. USP2004036710460.
  418. Misawa Kaori,JPX ; Ishihara Hiroyasu,JPX ; Mizuhara Hideki,JPX. Semiconductor devices with means to reduce contamination. USP2000116150725.
  419. Ishii Kazutoshi,JPX ; Inoue Naoto,JPX ; Maemura Koushi,JPX ; Nakanishi Shoji,JPX ; Kojima Yoshikazu,JPX ; Kadoi Kiyoaki,JPX ; Akiba Takao,JPX ; Moya Yasuhiro,JPX ; Kuhara Kentaro,JPX. Semiconductor dicing and assembling method. USP2000026022792.
  420. Bissey, Lucien J.. Semiconductor die assembly having leadframe decoupling characters and method. USP2003016504236.
  421. Jou Chewnpu,TWX. Semiconductor inductor. USP2001066242791.
  422. Kikushima Ken\ichi (Hitachi-seiwaryo ; 769 Shin-machi ; Ohme-shi ; Tokyo JPX) Yoshida Masaaki (Hitachi-wakakusaryo ; 657-5 Nogami ; Ohme-shi ; Tokyo JPX) Yabuki Shinobu (10-10-3-303 Kabe-machi ; Ohme. Semiconductor integrated circuit device. USP1995045410173.
  423. Noto Takayuki,JPX ; Oi Eiji,JPX ; Shiotsuki Yahiro,JPX ; Kato Kazuo,JPX ; Ohagi Hideki,JPX. Semiconductor integrated circuit device. USP2000026031257.
  424. Shinozaki, Masao; Nishimoto, Kenji; Akioka, Takashi; Kohara, Yutaka; Asari, Sanae; Miyata, Shusaku; Nakazato, Shinji. Semiconductor integrated circuit device. USP2005116963136.
  425. Tsuneoka Masatoshi (Ohme JPX) Horiuchi Mitsuaki (Hachioji JPX). Semiconductor integrated circuit device. USP1991105060050.
  426. Saito, Tatsuyuki; Ohashi, Naohumi; Imai, Toshinori; Noguchi, Junji; Tamaru, Tsuyoshi. Semiconductor integrated circuit device and a method of manufacturing the same. USP2004116818546.
  427. Ohashi Naofumi,JPX ; Yamaguchi Hizuru,JPX ; Noguchi Junji,JPX ; Owada Nobuo,JPX. Semiconductor integrated circuit device and fabrication process thereof. USP2001026184143.
  428. Owada Nobuo (Ohme JPX) Akimori Hiroyuki (Ohme JPX) Nitta Takahisa (Fuchuu JPX) Kobayashi Tohru (Iruma JPX) Sasabe Shunji (Iruma JPX) Kawaji Mikinori (Hino JPX) Kasahara Osamu (Hinode JPX). Semiconductor integrated circuit device and method of manufacturing the same. USP1991105060045.
  429. Tokunaga,Shinya; Furuya,Shigeki; Hinatsu,Yuuji. Semiconductor integrated circuit device and method of producing the same. USP2007017170115.
  430. Meguro Hideo (Tachikawa TX JPX) Yoshiura Yoshiaki (Irving TX) Itagaki Tatsuo (Hinode JPX) Uchida Ken (Higashiyamato JPX) Satoh Tsuneo (Tachikawa JPX) Ichihara Seiichi (Hachioji TX JPX) Nagasawa Koich. Semiconductor integrated circuit device and process for producing the same. USP1991105061985.
  431. Hayashi Yoshihiro,JPX ; Onodera Takahiro,JPX. Semiconductor integrated circuit device having minature multi-level wiring structure low in parasitic capacitance. USP1998025717251.
  432. Owada Nobuo (Ohme JPX) Oogaya Kaoru (Ohme JPX) Kobayashi Tohru (Iruma JPX) Kawaji Mikinori (Hino JPX). Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wir. USP1991065027188.
  433. Owada Nobuo (Ohme JPX) Oogaya Kaoru (Ohme JPX) Kobayashi Tohru (Iruma JPX) Kawaji Mikinori (Hino JPX). Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wir. USP1993065220199.
  434. Tadaki Yoshitaka (Hanno JPX) Murata Jun (Kunitachi JPX) Sekiguchi Toshihiro (Hidaka JPX) Aoki Hideo (Hamura JPX) Kawakita Keizo (Ome JPX) Uchiyama Hiroyuki (Higashimurayama JPX) Nishimura Michio (Tok. Semiconductor integrated circuit device including a memory device having memory cells with increased information storage. USP1996115578849.
  435. Sugiura Jun,JPX ; Tsuchiya Osamu,JPX ; Ogasawara Makoto,JPX ; Ootsuka Fumio,JPX ; Torii Kazuyoshi,JPX ; Asano Isamu,JPX ; Owada Nobuo,JPX ; Horiuchi Mitsuaki,JPX ; Tamaru Tsuyoshi,JPX ; Aoki Hideo,JP. Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same. USP1998075780882.
  436. Warwick William Arthur (Winchester EN). Semiconductor integrated circuit devices. USP1977054021838.
  437. Harada Shigeru,JPX ; Kishibe Kenji,JPX ; Ihisa Akira,JPX ; Mochizuki Hiroshi,JPX ; Tanaka Eisuke,JPX. Semiconductor integrated circuit interconnection structures and method of making the interconnection structures. USP2000106130481.
  438. Okumura Koichiro (Tokyo JPX). Semiconductor integrated circuits with specific pitch multilevel interconnections. USP1997055631478.
  439. Shimizu Kazuhiro,JPX ; Watanabe Hiroshi,JPX ; Takeuchi Yuji,JPX ; Aritome Seiichi,JPX ; Watanabe Toshiharu,JPX. Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the. USP2000126160297.
  440. Lee Kyu-Pil,KRX. Semiconductor memory device, and method for fabricating thereof. USP2001036200855.
  441. Thomas James R. (Woodlands TX) Nye Larry W. (Sherman TX) Brook Richard M. (Austin TX). Semiconductor non-corrosive metal overcoat. USP1994095346858.
  442. Iwasaki Hiroshi,JPX ; Aoki Hideo,JPX. Semiconductor package integral with semiconductor chip. USP1999045892273.
  443. Yen Daniel L. (Chu-Tung TWX). Semiconductor planarization process for submicron devices. USP1991035003062.
  444. Mercado, Lei L.; Sarihan, Vijay; Chung, Young Sir; Wang, James Jen-Ho; Prack, Edward R.. Semiconductor power device and method of formation. USP2003116646347.
  445. Hanes Maurice H. (Murrysville) Clarke Rowland C. (Bell Township) Driver Michael C. (Elizabeth Township PA). Semiconductor wafer with circuits bonded to a substrate. USP1993035198695.
  446. Yu Sun-il,KRX ; Kang Woo-tag,KRX. Semiconductor-on-insulator devices having insulating layers therein with self-aligned openings. USP2000106130457.
  447. Matloubian Mishel (Dallas TX). Sidewall channel stop process. USP1988064753896.
  448. Flagello Donis G. (Ridgefield CT) Wilczynski Janusz S. (Ossining NY) Witman David F. (Pleasantville NY). Simultaneous multiple level interconnection process. USP1989064840923.
  449. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd. Solder bump fabrication methods and structure including a titanium barrier layer. USP1998065767010.
  450. Cederbaum Carl (Paris FRX) Chanclou Roland (Perthes FRX) Combes Myriam (Evry FRX) Mone Patrick (Ponthierry FRX). Stacked conductive resistive polysilicon lands in multilevel semiconductor chips. USP1995015381046.
  451. Ling Peiching (San Jose CA). Structure and fabrication process of inductors on semiconductor chip. USP1996115576680.
  452. Farooq Mukta S. ; Farooq Shaji ; Hamel Harvey C. ; Knickerbocker John U. ; Rita Robert A. ; Stoller Herbert I.. Structure for a thin film multilayer capacitor. USP2000026023407.
  453. Lien Chuen-Der. Structure for fabricating a bonding pad having improved adhesion to an underlying structure. USP1998035723822.
  454. Schroeder Jack A. ; Monroe Conrad S.. Structure having flip-chip connected substrates. USP1998045742100.
  455. Hsu Chen-Chung,TWX. Structure of manufacturing an electrostatic discharge protective circuit for SRAM. USP2000016018183.
  456. Gaul Stephen Joseph ; Delgado Jose Avelino. Surface mount die by handle replacement. USP1998095807783.
  457. Schaefer William Jeffrey ; Kao Pai-Hsiang ; Kelkar Nikhil Vishwanath. Surface mount die: wafer level chip-scale package and process for making the same. USP2000066075290.
  458. Jones Robert E. (Saint Peters MO). Surface mounted component adaptor for interconnecting of surface mounted circuit components. USP1989104871317.
  459. Gaul Stephen Joseph (Melbourne FL). System for interconnecting stacked integrated circuits. USP1997105682062.
  460. Hingarh Hemraj (Saratoga CA) Asuncion Andres D. (Sunnyvale CA) Thomas Michael (Cupertino CA) Brown Robert (Palo Alto CA). Thick bus metallization interconnect structure to reduce bus area. USP1992055111276.
  461. Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A.. Thick plated interconnect and associated auxillary interconnect. USP2000026020640.
  462. Yuito Isamu (Hachiouji JPX) Moriwaki Eijin (Hachiouji JPX) Shiiki Kazuo (Kanagawa JPX) Hamakawa Yoshihiro (Koganei JPX) Takano Hisashi (Hachiouji JPX). Thin film magnetic head. USP1989114881144.
  463. Leedy Glenn J. (Montecito CA). Three dimensional semiconductor circuit structure with optical interconnection. USP1997065637907.
  464. Lin, Mou-Shiung. Top layers of metal for high performance IC's. USP2003126657310.
  465. Lin, Mou-Shiung. Top layers of metal for high performance IC's. USP2003096620728.
  466. Lin, Mou-Shiung. Top layers of metal for high performance IC's. USP2005116965165.
  467. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2007117294870.
  468. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008027329954.
  469. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008057372155.
  470. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008067384864.
  471. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008097422976.
  472. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2007117294871.
  473. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008057372085.
  474. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008057368376.
  475. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008067385291.
  476. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008047358610.
  477. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008107442969.
  478. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008077397135.
  479. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008127465975.
  480. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008097425764.
  481. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2009017482693.
  482. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008067385292.
  483. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008067388292.
  484. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008067382058.
  485. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008077396756.
  486. Lin,Mou Shiung. Top layers of metal for high performance IC's. USP2008117456100.
  487. Mou-Shiung Lin TW. Top layers of metal for high performance IC's. USP2002056383916.
  488. Marty Michel,FRX ; Jaouen Herve,FRX. Transformer for integrated circuits. USP2000026031445.
  489. Getselis Arkady (Staten Island NY) Tufano Anthony (North Massapequa NY). Turn knob lampholder. USP1996055514006.
  490. Burghartz Joachim Norbert (Shrub Oak NY) Jenkins Keith Aelwyn (Tarrytown NY) Ponnapalli Saila (Fishkill NY) Soyuer Mehmet (Yorktown Heights NY). Two-level spiral inductor structure having a high inductance to area ratio. USP1997085656849.
  491. Moslehi Mehrdad M.. Ultra high-speed chip interconnect using free-space dielectrics. USP2000096124198.
  492. Moslehi Mehrdad M.. Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics. USP2000016016000.
  493. Liu Donghang. Ultra-small capacitor array. USP2001116324048.
  494. Sebesta, Robert David; Wilson, James Warren. Variable thickness pads on a substrate surface. USP2005056900545.
  495. Chen,Xiangdong; Wang,Geng; Li,Yujun; Ouyang,Qiqing C.. Vertical MOSFET with dual work function materials. USP2007117294879.
  496. Williams Richard K. ; Kasem Mohammad. Vertical power MOSFET having thick metal layer to reduce distributed resistance. USP2000056066877.
  497. Hsuan Min-Chih,TWX ; Feng Taisheng,TWX ; Han Charlie,TWX. Wafer level integrated circuit structure and method of manufacturing the same. USP2001046214630.
  498. Lin Mou-Shiung,TWX. Wafer scale packaging scheme. USP2000086103552.
  499. Mou-Shiung Lin TW. Wafer scale packaging scheme. USP2002026350705.
  500. Test, Howard R.; Amador, Gonzalo; Subido, Willmar E.. Wire bonding process for copper-metallized integrated circuits. USP2004106800555.
  501. Cutting, Lawrence Richard; Gaudiello, John Gerard; Matienzo, Luis Jesus; Murdeshwar, Nikhil Mohan. Wire bonding to dual metal covered pad surfaces. USP2004076759597.
  502. Ishikawa Hiraku,JPX. Wiring layer in semiconductor device. USP1999045894170.