이 특허에 인용된 특허 (159)

1. Bohr, Mark T., Alternate bump metallurgy bars for power and ground routing.

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2. Andricacos Panayotis Constantinou ; Datta Madhav ; Horkans Wilma Jean ; Kang Sung Kwon ; Kwietniak Keith Thomas, Barrier layers for electroplated SnPb eutectic solder joints.

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3. Ichikawa Matsuo,JPX, Bonding pad structures for semiconductor integrated circuits.

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4. Fan, Yang-Tung; Chu, Cheng-Yu; Fan, Fu-Jier; Lin, Shih-Jane; Peng, Chiou-Shian; Chen, Yen-Ming; Lin, Kuo-Wei, Bumping process to increase bump height and to create a more robust bump structure.

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5. Mou-Shiung Lin TW, Capacitor for high performance system-on-chip using post passivation process structure.

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6. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.

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7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.

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8. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.

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9. Takeyuki Itabashi JP, Circuit board, a method for manufacturing same, and a method of electroless plating.

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10. Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.

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11. Islam Rabiul ; Gelatos Avgerinos V. ; Lucas Kevin ; Filipiak Stanley M. ; Venkatraman Ramnath, Copper interconnect structure and method of formation.

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12. Mitwalsky Alexander R. ; Chen Tze-Chiang, Crack stops.

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13. Chen Sen-Fu,TWX ; Wu Jie-Shing,TWX ; Chen Fang-Cheng,TWX ; Lee Tsung-Tser,TWX, Damage free passivation layer etching process.

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14. Chittipeddi Sailesh ; Cochran William T. ; Smooha Yehuda, Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein.

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15. Shroff, Mehul; Benard, Gerald G.; Grigg, Philip, Dielectric between metal structures and method therefor.

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16. Fillion Raymond A. (Niskayuna NY) Wildi Eric J. (Niskayuna NY) Korman Charles S. (Schenectady NY) El-Hamamsy Sayed-Amr (Schenectady NY) Gasworth Steven M. (Glenville NY) DeVre Michael W. (Scotia NY) , Direct stacked and flip chip power semiconductor device structures.

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17. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method.

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18. Chittipeddi, Sailesh; Cochran, William Thomas; Smooha, Yehuda, Dual damascene bond pad structure for lowering stress and allowing circuitry under pads.

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19. Kang-Cheng Lin TW, Dual damascene process and structure with dielectric barrier layer.

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20. Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX), ESD protection structure using LDMOS diodes with thick copper interconnect.

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21. Jacobs Scott L. (Apex NC), Extended integration semiconductor structure with wiring layers.

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22. Saran, Mukul; Martin, Charles A.; Cox, Ronald H., Fine pitch system and method for reinforcing bond pads in semiconductor devices.

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23. Liang Mike, Flip chip bump distribution on die.

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24. Shenoy Jayarama N. ; Findley Paul, Flip chip circuit arrangement with redistribution layer that minimizes crosstalk.

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25. Fulcher Edwin (Palo Alto CA), Flip chip package with reduced number of package layers.

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26. Takada Norimasa (Tokyo JPX), Flip chip type semiconductor device.

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27. Lu, Hsueh-Chung Shelton; Chang, Kenny; Huang, Jimmy, Flip-chip bump arrangement for decreasing impedance.

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28. Hsu, Chi-Hsing, Flip-chip die and flip-chip package substrate.

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29. Kumar Nalin (Austin TX), Forming via holes in a multilevel substrate in a single step.

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30. Schroen Walter H. ; Archer Judith S. ; Terrill Robert E., Fully hermetic semiconductor chip, including sealed edge sides.

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31. Wachtler, Kurt P.; Walter, David N.; Mowatt, Larry J., HID land grid array packaged device having electrical and optical interconnects.

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32. Wollesen Donald L. (Saratoga CA), High conductivity interconnection line.

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33. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA), High-density, multi-level interconnects, flex circuits, and tape for TAB.

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34. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA), High-density, multi-level interconnects, flex circuits, and tape for tab.

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35. Mou-Shiung Lin TW, Inductor structure for high performance system-on-chip using post passivation process.

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36. Cronin John Edward, Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same.

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37. Kloen Hendrik K.,NLX ; Huiskamp Lodewijk P.,NLX, Integrated circuit device.

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38. Nakanishi Keiichirou (Kokubunji JPX) Yamada Minoru (Hanno JPX) Saitoh Tatsuya (Kokubunji JPX) Yamamoto Kazumichi (Kokubunji JPX), Integrated circuit device having an ic chip mounted on the wiring substrate and having suitable mutual connections betwe.

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39. Lamson Michael A. (Van Alstyne TX) Edwards Darvin R. (Dallas TX), Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof.

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40. Gregoire Francois ; Madurawe Raminda ; Thalapaneni Guru, Integrated circuit pad structures.

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41. Efland, Taylor R.; Abbott, Donald C.; Bucksch, Walter; Corsi, Marco; Shen, Chi-Cheong; Erdeljac, John P.; Hutter, Louis N.; Mai, Quang X.; Wagensohner, Konrad; Williams, Charles E.; Buschbom, Milton , Integrated circuit with bonding layer over active circuitry.

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42. Shen Chi-Cheong ; Abbott Donald C. ; Bucksch Walter,DEX ; Corsi Marco ; Efland Taylor Rice ; Erdeljac John P. ; Hutter Louis Nicholas ; Mai Quang ; Wagensohner Konrad,DEX ; Williams Charles Edward, Integrated circuit with bonding layer over active circuitry.

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43. Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT), Integrated memory cube, structure and fabrication.

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44. Ahmad Umar M. U. (Both of Hopewell Junction NY) Kumar Ananda H. (Both of Hopewell Junction NY) Perfecto Eric D. (Wappingers Falls NY) Prasad Chandrika (Wappingers Falls NY) Purushothaman Sampath (Yor, Interconnect structure having improved metallization.

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45. David V. Horak ; William A. Klaasen ; Thomas L. McDevitt ; Mark P. Murray ; Anthony K. Stamper, Interconnection structure and method for fabricating same.

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46. Yamazaki, Shunpei; Tanaka, Koichiro; Hiroki, Masaaki, Laser annealing apparatus and semiconductor device manufacturing method.

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47. Wollesen Donald L., Low capacitance interconnection.

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48. Brintzinger, Axel, Manufacturing of a corrosion protected interconnect on a substrate.

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49. Brown Vernon L. ; Magera Yaroslaw A., Metallization and termination process for an integrated circuit chip.

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50. Cheung Robin W. ; Ting Chiu H., Metallized interconnection structure and method of making the same.

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51. Tomasi Peter A. ; Zhao Tong ; St. Angel Lindo ; Schellinger Michael J. ; Nguyen Dien N. ; Bradley Wayne H., Method and apparatus for reducing current consumption.

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52. Okada, Takako, Method and apparatus for simulating manufacturing, electrical and physical characteristics of a semiconductor device.

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53. Mistry Addi Burjorji ; Sarihan Vijay ; Kleffner James H. ; Carney George F., Method and apparatus for stress relief in solder bump formation on a semiconductor device.

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54. Bojkov, Christo P.; Arbuthnot, Diane L.; Kunesh, Robert F., Method for chemical etch control of noble metals in the presence of less noble metals.

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55. Gehman ; Jr. John B. (Scottsdale AZ) O\Connell Richard P. (Scottsdale AZ), Method for connection of signals to an integrated circuit.

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56. Yamada Yoshiaki,JPX, Method for fabricating a semiconductor device having a refractory metal pillar for electrical connection.

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57. Boyd Melissa D. (Corvallis OR), Method for forming a conductive pattern on an integrated circuit.

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58. Lee Jia-Sheng,TWX, Method for forming a thin-film resistor.

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59. Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.

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60. Leu, Jihperng; Wu, Chih-I; Zhou, Ying; Kloster, Grant M., Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics.

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61. Gansauge Peter (Boeblingen DEX) Kreuter Volker (Schoenaich DEX) Schettler Helmut (Dettenhausen DEX), Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer.

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62. Hendel Rudi (26 Ridge Rd. Summit NJ 07901) Levinstein Hyman (132 Robbins Ave. Berkeley Heights NJ 07974), Method for planarization of submicron vias and the manufacture of semiconductor integrated circuits.

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63. Leung Pak K.,CAX ; Emesh Ismail T.,CAX, Method of adding on chip capacitors to an integrated circuit.

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64. Robl, Werner; Goebel, Thomas; Brintzinger, Axel Christoph; Friese, Gerald, Method of eliminating back-end rerouting in ball grid array packaging.

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65. Gardner Donald S., Method of fabricating a barrier against metal diffusion.

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66. Yamaguchi, Yoshihide; Tenmei, Hiroyuki; Hozoji, Hiroshi; Kanda, Naoya, Method of fabricating a wafer level chip size package utilizing a maskless exposure.

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67. Kumar Nalin (Austin TX), Method of fabricating electrical components in high density substrates.

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68. Sakamoto, Tatsuya, Method of fabricating semiconductor device.

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69. Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A., Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect.

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70. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.

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71. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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72. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines.

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73. Kohyama Yusuke (Yokosuka JPX), Method of manufacturing a semiconductor device.

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74. Tokushige, Ryoji; Takai, Nobuyuki; Shinogi, Hiroyuki; Ono, Seiichi, Method of manufacturing a semiconductor device.

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75. Yamada Yoshiaki,JPX, Method of manufacturing a semiconductor device using a silicon fluoride oxide film.

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76. Peters Johannes S. (Nijmegen NLX), Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided o.

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77. Ho Paul Kwok Keung,SGX ; Zhou Mei Sheng,SGX ; Gupta Subhash,SGX, Method to create a controllable and reproducible dual copper damascene structure.

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78. Smoak, Richard C., Method to improve the reliability of thermosonic gold to aluminum wire bonds.

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79. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.

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80. Steinhardt Paul J. (1000 Cedar Grove Rd. Wynnewood PA 19096) Taylor Philip (7801 Bustleton Ave. Philadelphia PA 19152), Methods and apparatus for eliminating Moire\interference using quasiperiodic patterns.

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81. Kie Y. Ahn ; Leonard Forbes, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.

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82. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.

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83. Cronin John Edward (Milton VT) Howell Wayne John (Williston VT) Kalter Howard Leo (Colchester VT) Marmillion Patricia Ellen (Colchester VT) Palagonia Anthony (Underhill VT) Pierson Bernadette Ann (So, Methods for precise definition of integrated circuit chip edges.

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84. Lin, Mou-Shiung; Ting, Tah-Kang Joseph, Methods of IC rerouting option for multiple package system applications.

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85. Kim, Sarah E.; Lee, Kevin J.; George, Anna M., Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow.

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86. Vu, Quat T.; Ton, Tuy T.; Towle, Steven, Microelectronic device having signal distribution functionality on an interfacial layer thereof.

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87. Nguyen Chanh N. ; Nguyen Nguyen Xuan ; Le Minh V., Modulation-doped field-effect transistors and fabrication processes.

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88. Laurent Basteres FR; Ahmed Mhani FR; Fran.cedilla.ois Valentin FR; Jean-Michel Karam FR, Monolithic integrated circuit incorporating an inductive component and process for fabricating such an integrated circuit.

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89. Mototsugu Okushima JP, Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor.

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90. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R., Personalization structure for semiconductor devices.

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91. Tung, Francisca, Pillar connections for semiconductor chips and method of manufacture.

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92. Pasch Nicholas F., Polymeric dielectric layers having low dielectric constants and improved adhesion to metal lines.

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93. Lin,Mou Shiung; Chou,Chien Kang; Chou,Chiu Ming, Post passivation interconnection process and structures.

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94. Mou-Shiung Lin TW; Jin-Yuan Lee TW, Post passivation interconnection schemes on top of the IC chips.

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95. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.

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96. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.

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97. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.

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98. E. Henry Stevens, Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece.

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99. Vivian W. Ryan, Process for fabricating copper interconnect for ULSI integrated circuits.

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100. Sun Shih-Wei (Austin TX) Kosa Yasunobu (Austin TX) Yeargain John R. (Austin TX), Process for forming a structure which electrically shields conductors.

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101. Flynn Todd M. ; Argento Christopher W. ; Larsen Larry J., Process for forming an electrical device.

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102. Ikeda Osamu,JPX ; Nakamura Yoshio,JPX, Process for producing electrode for semiconductor element and semiconductor device having the electrode.

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103. Quinn ; Daniel J. (Carrollton TX) Mulholland Wayne A. (Plano TX) Bond Robert H. (Carrollton TX) Olla Michael A. (Flower Mound TX) Cupples Jerry S. (Carrollton TX) Tsitovsky Ilya L. (Farmers Branch TX, Process of forming integrated circuits with contact pads in a standard array.

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104. Dangelo Carlos (Los Gatos CA), Programmable microsystems in silicon.

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105. Leibovitz Jacques ; Yu Park-Kee ; Zhu Ya Yun ; Cobarruviaz Maria L. ; Swindlehurst Susan J. ; Chang Cheng-Cheng ; Scholz Kenneth D., Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps.

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106. Kumamoto, Nobuhisa; Samejima, Katsumi, Semiconductor chip and production process therefor.

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107. Wang, Kun-Chih; Wu, Bing-Chang, Semiconductor chip capable of implementing wire bonding over active circuits.

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108. Hajime Iizuka JP, Semiconductor device.

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109. Tahara, Iwao; Mihara, Ichiro; Aoki, Yutaka, Semiconductor device.

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110. Nishiyama Akira,JPX, Semiconductor device and a method of manufacturing the same.

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111. Shigeru Harada JP; Takeru Matsuoka JP; Hiroki Takewaka JP, Semiconductor device and fabrication process therefor.

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112. Shimizu, Hironobu; Fujimoto, Koji; Horio, Masahiro, Semiconductor device and manufacturing method thereof.

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113. Kikuchi, Hidekazu, Semiconductor device and method for manufacturing.

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114. Yoshizawa Shunichi,JPX, Semiconductor device and method for manufacturing the same.

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115. Wada, Junichi; Sakata, Atsuko; Katata, Tomio; Usui, Takamasa; Hasunuma, Masahiko; Shibata, Hideki; Kaneko, Hisashi; Hayasaka, Nobuo; Okumura, Katsuya, Semiconductor device and method of manufacturing the same.

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116. Sasaki Keiichi,JPX ; Kunishima Iwao,JPX, Semiconductor device having WNF film and method of manufacturing such a device.

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117. Yong, Lois E.; Harper, Peter R.; Tran, Tu Anh; Metz, Jeffrey W.; Leal, George R.; Dinh, Dieu Van, Semiconductor device having a bond pad and method therefor.

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118. Hosomi Eiichi,JPX ; Takubo Chiaki,JPX ; Tazawa Hiroshi,JPX ; Shibasaki Koji,JPX, Semiconductor device having a bump electrode connected to an inner lead.

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119. Kim Seong Jin,KRX, Semiconductor device having a bump structure and test electrode.

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120. Aoki, Yutaka, Semiconductor device having a chip size package including a passive element.

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121. Suminoe,Shinji; Nakanishi,Hiroyuki; Ishio,Toshiya; Iwazaki,Yoshihide; Mori,Katsunobu, Semiconductor device having a leading wiring layer.

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122. Irinoda Mitsugu,JPX, Semiconductor device having a minute contact hole.

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123. Aoyama Masaharu (Fujisawa JPX) Abe Masahiro (Yokohama JPX) Ajima Takashi (Kamakura JPX) Yonezawa Toshio (Kitakyushu JPX), Semiconductor device having a multilayer wiring structure using a polyimide resin.

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124. Ohkura Yoshiyuki,JPX ; Harada Hideki,JPX, Semiconductor device having a porous insulation film.

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125. Downey, Susan H.; Miller, James W.; Hall, Geoffrey B., Semiconductor device having a wire bond pad and method therefor.

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126. Toyosawa, Kenji; Ono, Atsushi; Chikawa, Yasunori; Sakaguchi, Nobuhisa; Nakamura, Nakae; Nakata, Yukinori, Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film.

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127. Hidetoshi Koike JP, Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire.

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128. Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX, Semiconductor device having an element with circuit pattern thereon.

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129. Wenzel James F. (Austin TX) Chopra Mona A. (Austin TX) Foster Stephen W. (Dripping Springs TX), Semiconductor device having built-in high frequency bypass capacitor.

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130. Sato Susumu (Tokyo JPX) Shiba Hiroshi (Tokyo JPX), Semiconductor device having bump terminal electrodes.

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131. Hyakutake Yasuhito,JPX, Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof.

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132. Ueda Tetsuya,JPX ; Tamaoka Eiji,JPX ; Aoi Nobuo,JPX, Semiconductor device having multilevel interconnection structure and method for fabricating the same.

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133. Homma, Soichi; Miyata, Masahiro; Ezawa, Hirokazu, Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same.

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134. Amishiro Hiroyuki,JPX ; Igarashi Motoshige,JPX, Semiconductor device including a plurality of interconnection layers.

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135. Matsuki Hirohisa,JPX ; Kado Kenichi,JPX ; Watanabe Eiji,JPX ; Imamura Kazuyuki,JPX ; Yurino Takahiro,JPX, Semiconductor device with pad structure.

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136. Anzai,Noritaka, Semiconductor device with signal line having decreased characteristic impedance.

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137. Morozumi, Yukio, Semiconductor devices and methods for manufacturing the same.

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138. Ishii Kazutoshi,JPX ; Inoue Naoto,JPX ; Maemura Koushi,JPX ; Nakanishi Shoji,JPX ; Kojima Yoshikazu,JPX ; Kadoi Kiyoaki,JPX ; Akiba Takao,JPX ; Moya Yasuhiro,JPX ; Kuhara Kentaro,JPX, Semiconductor dicing and assembling method.

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139. Shinozaki, Masao; Nishimoto, Kenji; Akioka, Takashi; Kohara, Yutaka; Asari, Sanae; Miyata, Shusaku; Nakazato, Shinji, Semiconductor integrated circuit device.

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140. Saito, Tatsuyuki; Ohashi, Naohumi; Imai, Toshinori; Noguchi, Junji; Tamaru, Tsuyoshi, Semiconductor integrated circuit device and a method of manufacturing the same.

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141. Ohashi Naofumi,JPX ; Yamaguchi Hizuru,JPX ; Noguchi Junji,JPX ; Owada Nobuo,JPX, Semiconductor integrated circuit device and fabrication process thereof.

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142. Meguro Hideo (Tachikawa TX JPX) Yoshiura Yoshiaki (Irving TX) Itagaki Tatsuo (Hinode JPX) Uchida Ken (Higashiyamato JPX) Satoh Tsuneo (Tachikawa JPX) Ichihara Seiichi (Hachioji TX JPX) Nagasawa Koich, Semiconductor integrated circuit device and process for producing the same.

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143. Harada Shigeru,JPX ; Kishibe Kenji,JPX ; Ihisa Akira,JPX ; Mochizuki Hiroshi,JPX ; Tanaka Eisuke,JPX, Semiconductor integrated circuit interconnection structures and method of making the interconnection structures.

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144. Iwasaki Hiroshi,JPX ; Aoki Hideo,JPX, Semiconductor package integral with semiconductor chip.

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145. Mercado, Lei L.; Sarihan, Vijay; Chung, Young Sir; Wang, James Jen-Ho; Prack, Edward R., Semiconductor power device and method of formation.

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146. Yu Sun-il,KRX ; Kang Woo-tag,KRX, Semiconductor-on-insulator devices having insulating layers therein with self-aligned openings.

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147. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd, Solder bump fabrication methods and structure including a titanium barrier layer.

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148. Schaefer William Jeffrey ; Kao Pai-Hsiang ; Kelkar Nikhil Vishwanath, Surface mount die: wafer level chip-scale package and process for making the same.

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149. Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A., Thick plated interconnect and associated auxillary interconnect.

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150. Scheunemann, Karl-Heinz; Knolle, Jochen; Peyman, Amuschirwan; Will, David William; Carniato, Denis; Gourvest, Jean-Francois; Gadek, Thomas; McDowell, Robert; Bodary, Sarah Catherine; Cuthbertson, Rob, Thienyl substituted acylguanidines as inhibitors of bone resorption and vitronectin receptor antagonists.

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151. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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152. Mou-Shiung Lin TW, Top layers of metal for high performance IC's.

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153. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.

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154. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

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155. Sebesta, Robert David; Wilson, James Warren, Variable thickness pads on a substrate surface.

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156. Williams Richard K. ; Kasem Mohammad, Vertical power MOSFET having thick metal layer to reduce distributed resistance.

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157. Lin Mou-Shiung,TWX, Wafer scale packaging scheme.

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