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Integrated circuit and method for fabricating the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
출원번호 US-0766805 (2007-06-22)
등록번호 US8022552 (2011-09-06)
발명자 / 주소
  • Lin, Mou-Shiung
  • Lee, Jin-Yuan
출원인 / 주소
  • Megica Corporation
대리인 / 주소
    McDermott Will & Emery, LLP
인용정보 피인용 횟수 : 7  인용 특허 : 66

초록

A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5μm and 27 μm over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace

대표청구항

What is claimed is: 1. An IC chip comprising:a semiconductor substrate;a transistor having a portion in said semiconductor substrate;a first dielectric layer over said semiconductor substrate;a first patterned metal layer over said first dielectric layer;a second dielectric layer over said first pat

이 특허에 인용된 특허 (66)

  1. Bohr, Mark T., Alternate bump metallurgy bars for power and ground routing.
  2. Farrar, Paul A., Barrier layer associated with a conductor layer in damascene structures.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  4. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  5. Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.
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  14. Lamson Michael A. (Van Alstyne TX) Edwards Darvin R. (Dallas TX), Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof.
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  20. Lin Mou-Shiung,TWX, Method for forming high performance system-on-chip using post passivation process.
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  31. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection process and structures.
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  36. Lin, Mou-Shiung; Lei, Ming-Ta; Lee, Jin-Yuan; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
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  38. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
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  51. Wakabayashi, Takeshi; Mihara, Ichiro, Semiconductor device having reduced number of external pad portions.
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  54. Harada Shigeru (Hyogo JPX) Endoh Takemi (Hyogo JPX) Ishida Tomohiro (Hyogo JPX), Semiconductor device with bonding pad electrode.
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  57. Shinozaki, Masao; Nishimoto, Kenji; Akioka, Takashi; Kohara, Yutaka; Asari, Sanae; Miyata, Shusaku; Nakazato, Shinji, Semiconductor integrated circuit device.
  58. Ohashi Naofumi,JPX ; Yamaguchi Hizuru,JPX ; Noguchi Junji,JPX ; Owada Nobuo,JPX, Semiconductor integrated circuit device and fabrication process thereof.
  59. Iwasaki Hiroshi,JPX ; Aoki Hideo,JPX, Semiconductor package integral with semiconductor chip.
  60. Mercado, Lei L.; Sarihan, Vijay; Chung, Young Sir; Wang, James Jen-Ho; Prack, Edward R., Semiconductor power device and method of formation.
  61. Chou,Chiu Ming; Lin,Mou Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  62. Takeshita Shuji (Kawasaki JPX), Thin film circuit board manufacturing process.
  63. Mou-Shiung Lin TW, Top layers of metal for high performance IC's.
  64. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  65. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  66. Lin,Mou Shiung; Chen,Michael; Chou,Chien Kang; Chou,Mark, Wirebond pad for semiconductor chip or wafer.

이 특허를 인용한 특허 (7)

  1. Lin, Mou-Shiung, Chip package and method for fabricating the same.
  2. Gordon, Roy Gerald; Kim, Hoon; Bhandari, Harish, Cobalt nitride layers for copper interconnects and methods for forming them.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  4. Pendse, Rajendra D.; Ouyang, Chien; Joshi, Mukul, Integrated circuit system with stress redistribution layer and method of manufacture thereof.
  5. Holland, Phillip; Liu, Rong; Sharma, Umesh; Marreiro, David D; Liou, Der Min; Shastri, Sudhama C, Method of manufacturing a semiconductor component and structure.
  6. Shao, Wei; Yi, Wanbing; Gong, Shunqiang; Zhu, Chao; Tan, Juan Boon, Semiconductor device and method of forming thereof.
  7. Morita, Takeshi; Kato, Shinjiro; Akino, Masaru; Imura, Yukihiro, Semiconductor device and method of manufacturing a semiconductor device.
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