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Condition code flag emulation for program code conversion 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
출원번호 US-0957343 (2007-12-14)
등록번호 US8024555 (2011-09-06)
우선권정보 GB-2002-202728.2(2002-02-06)
발명자 / 주소
  • Sandham, John H.
  • North, Geraint M.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Matthew B., Talpis
인용정보 피인용 횟수 : 1  인용 특허 : 67

초록

An emulator allows subject code written for a subject processor having subject processor registers and condition code flags to run in a non-compatible computing environment. The emulator identifies and records parameters of instructions in the subject code that affect status of the subject condition

대표청구항

What is claimed is: 1. Computer software resident on a tangible computer readable storage medium and operable when executed by a computer to perform program code conversion comprising the steps of:(a) establishing one or more abstract registers, each corresponding to a unique flag parameter (operand

이 특허에 인용된 특허 (67)

  1. Pegatoquet, Alain; Auguin, Michel; Sohier, Olivier, Apparatus and method for annotating an intermediate representation of an application source code.
  2. Kranich Uwe,DEX ; Christie David S., Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks.
  3. Rappoport, Lihu; Jourdan, Stephan J.; Ronen, Ronny, Cache structure for storing variable length data.
  4. Kosche, Nicolai, Compiler-based cache line optimization.
  5. Dwyer ; III Harry, Computer system having organization for multiple condition code setting and for testing instruction out-of-order.
  6. Aizikowitz Nava E.,ILX ; Bar-Haim Roy N.,ILX ; Edelstein Orit,ILX ; Prosser Edward Curtis ; Roediger Robert Ralph, Cooperation of global and local register allocators for better handling of procedures.
  7. Brewer Kevin J. (Kokomo IN) Linke Scott L. (Flora IN), Data processing system with condition code architecture for executing single instruction range checking and limiting ope.
  8. Davidian Gary G. (Mountain View CA), Decoding guest instruction to directly access emulation routines that emulate the guest instructions.
  9. David A. Egolf, Different word size multiprocessor emulation.
  10. Hilgendorf Rolf,DEX ; Schwermer Hartmut,DEX ; Soell Werner,DEX, Dynamic conversion between different instruction codes by recombination of instruction elements.
  11. Walters Chad Perry ; Brown Jorg Anthony, Dynamic cross-compilation system and method.
  12. Richard A. Lethin ; Joseph A. Bank, III ; Charles D. Garrett ; Mikayo Wada JP; Mitsuo Sakurai JP, Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method.
  13. Morris, Dale C.; Ross, Jonathan K.; Hays, James O.; Huck, Jerome C., Emulated branch effected by trampoline mechanism.
  14. Swoboda Gary L. (Sugar Land TX) Daniels Martin D. (Houston TX) Coomes Joseph A. (Missouri City TX), Emulation devices, systems and methods utilizing state machines.
  15. Swoboda, Gary L.; Daniels, Martin D.; Coomes, Joseph A., Emulation devices, systems and methods utilizing state machines.
  16. Swoboda Gary L. ; Ing-Simmons Nicholas K.,GB2 ; Simpson Richard David,GB2, Emulation devices, systems, and methods.
  17. Adachi Shigemi (Owariasahi JPX) Nakaosa Yoshitake (Yokohama JPX) Fujioka Yoshiki (Aichi JPX), Emulation method.
  18. Le, Bich-Cau, Emulation system that uses dynamic binary translation and permits the safe speculation of trapping operations.
  19. Shimizu Hisayoshi (Kodaira JPX), Emulation techniques giving necessary information to a microcomputer to perform software debug and system debug even for.
  20. Ackerman Dennis F. (Boynton Beach FL) Desai Himanshu H. (Boca Raton FL) Gupta Ram K. (Boca Raton FL) Srinivasan Ravi R. (Boca Raton FL), Exception handling method and apparatus for a microkernel data processing system.
  21. Yates John S. ; Robinson Scott G. ; Herdeg Mark, Fast translation and execution of a computer program on a non-native architecture by use of background translator.
  22. Kahle James Allan ; Mallick Soummya, Indirect unconditional branches in data processing system emulation mode.
  23. Srivastava Amitabh, Link time optimization with translation to intermediate program and following optimization techniques including program.
  24. Chernoff Anton ; Yates John S., Means and apparatus for maintaining condition codes in an unevaluated state.
  25. Brauch, Rupert; Dunn, David A., Mechanism for software register renaming and load speculation in an optimizer.
  26. Bennett James ; Anderson Mark ; Na Choon Piaw ; Hastings Reed, Method and apparatus for accurate profiling of computer programs.
  27. Bergner, Peter Edward; Prosser, Edward Curtis, Method and apparatus for allocating registers during code compilation using different spill strategies to evaluate spill cost.
  28. Breternitz ; Jr. Mauricio ; Smith Roger Alan, Method and apparatus for code translation optimization.
  29. Rajiv Mirani ; Bruce A. Olsen ; Harish Patil, Method and apparatus for debugging of optimized code using emulation.
  30. Goettelmann John C. (Point Pleasant NJ) Macey Christopher J. (Red Bank NJ), Method and apparatus for direct conversion of programs in object code form between different hardware architecture compu.
  31. Goettelmann John C. (Point Pleasant NJ) Macey Christopher J. (Red Bank NJ), Method and apparatus for direct conversion of programs in object code form between different hardware architecture compu.
  32. Goettelmann John C. (Point Pleasant NJ) Macey Christopher J. (Red Bank NJ), Method and apparatus for direct conversion of programs in object code from between different hardware architecture compu.
  33. Krishnaswamy Umesh, Method and apparatus for handling asynchronous exceptions in a dynamic translation system.
  34. Yates, John S.; Tye, Steven Tony, Method and apparatus for maintaining translated routine stack in a binary translation environment.
  35. Farber Yaron,ILX ; Sheaffer Gad,ILX ; Valentine Robert,ILX, Method and apparatus for merging binary translated basic blocks of instructions.
  36. Yates John S. ; Tye Steven Tony ; Hookway Raymond J., Method and apparatus for performing binary translation.
  37. John S. Yates ; Steven Tony Tye ; Raymond J. Hookway, Method and apparatus for performing binary translation method and apparatus for performing binary translation.
  38. Sheaffer, Gad S., Method and apparatus for pre-processing instructions for a processor.
  39. Farber Yaron,INX ; Levhari Yossi,ILX ; Baraz Leonid,ILX ; Ladiray Gallia,ILX, Method and apparatus for translating a conditional instruction compatible with a first instruction set architecture (IS.
  40. Shah Lacky V. ; Mattson ; Jr. James S. ; Buzbee William B., Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance.
  41. Kahle James Allan ; Mallick Soummya, Method and system for processing branch instructions during emulation in a data processing system.
  42. Callahan ; II Charles David, Method and system for target register allocation.
  43. Radigan Jim J., Method for determining the set of variables that may be ambiguously defined at a point in a computer program.
  44. Choi, Jong-Deok; Gupta, Manish; Serrano, Mauricio J.; Sreedhar, Vugranam C.; Midkiff, Samuel Pratt, Method for optimizing locks in computer programs.
  45. Adl-Tabatabai Ali-Reza, Method for performing dynamic optimization of computer code.
  46. Alan L. Davis ; Jonathan F. Humphreys ; Todd M. Snider ; Raj Kanagasabai, Method for translating between source and target code with heterogenous register sets.
  47. Geva, Robert Y., Method of constructing and unrolling speculatively counted loops.
  48. Ng John Shek-Luen, Method of, system for, and computer program product for providing improved code motion and code redundancy removal using extended global value numbering.
  49. Agnew Palmer W. (Owego NY) Buonomo Joseph P. (Endicott NY) Houghtalen Steven R. (Endicott NY) Kellerman Anne S. (Endicott NY) Losinger Raymond E. (Endicott NY) Valashinas James W. (Endicott NY), Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof.
  50. Scalzi Casper Anthony ; Schwarz Eric Mark ; Starke William John ; Urquhart James Robert ; Westcott Douglas Wayne, Preprocessing of stored target routines for emulating incompatible instructions on a target processor.
  51. Volkonsky, Vladimir Y.; Ostanevich, Alexander Y.; Sushentsov, Alexander L., Profile driven code motion and scheduling.
  52. Kensuke Odani JP; Akira Tanaka JP; Shuichi Takayama JP; Ryoichiro Koshimura JP, Program conversion apparatus for constant reconstructing VLIW processor.
  53. Scantlin Henry L. (Hermosa Beach CA), RISC architecture computer configured for emulation of the instruction set of a target computer.
  54. Aizikowitz Nava Arela,ILX ; Asnash Liviu,ILX ; Bar-Haim Roy,ILX ; Prosser Edward Curtis ; Roediger Robert Ralph ; Schmidt William Jon, Register allocation method and apparatus for gernerating spill code as a function of register pressure compared to dual.
  55. Trimberger Stephen M., Reprogrammable instruction set accelerator.
  56. Blomgren James S. ; Richter David E., Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets.
  57. Morley John E., Software emulation system with dynamic translation of emulated instructions for increased processing speed.
  58. Cohn Robert ; Adler Michael C. ; Lowney Paul Geoffrey, Software mechanism for reducing exceptions generated by speculatively scheduled instructions.
  59. Robinson Scott G., System and method for achieving object method transparency in a multi-code execution environment.
  60. Doshi Gautam B. ; Markstein Peter ; Karp Alan H. ; Huck Jerome C. ; Colon-Bonet Glenn T. ; Morrison Michael, System and method for deferring exceptions generated during speculative execution.
  61. Craig Chambers ; Susan J. Eggers ; Brian K. Grant ; Markus Mock ; Matthai Philipose, System and method for performing selective dynamic compilation using run-time information.
  62. Shah Lacky V. ; Mattson ; Jr. James S. ; Buzbee William B., System, method, and product for memory management in a dynamic translator.
  63. Goettelmann John Charles ; Hiller Ronald George ; Krantzler Irvan Jay ; Macey Christopher James ; Tuomenoksa Mark Logan, Technique for executing translated software.
  64. Benson Thomas R. (Hollis NH), Tracking condition codes in translation code for different machine architectures.
  65. Sites Richard Lee (Menlo Park CA), Translating, executing, and re-translating a computer program for finding and translating program code at unknown progra.
  66. Buzbee William B. ; Burch Carl D., Use of dynamic translation to provide breakpoints in non-writeable object code.
  67. Shmid, Alexander V.; Naumov, Viatcheslav V., Virtual machines in OS/390 for execution of any guest system.

이 특허를 인용한 특허 (1)

  1. Mihocka, Darek Josip, Arithmetic lazy flags representation for emulation.
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