$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Language and templates for use in the design of semiconductor products 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0122307 (2008-05-16)
등록번호 US8037448 (2011-09-28)
발명자 / 주소
  • Youngman, Todd Jason
  • Nordman, John Emery
출원인 / 주소
  • LSI Corporation
대리인 / 주소
    Westman, Champlin & Kelly, P.A.
인용정보 피인용 횟수 : 1  인용 특허 : 47

초록

During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby

대표청구항

What is claimed is: 1. A template engine, at least partially stored on a computer-readable memory and comprising:(a) means to read a plurality of resources available from a selected application set;(b) means to input a user's specification; and(c) means to generate a plurality of shells allocating t

이 특허에 인용된 특허 (47)

  1. Schmitz Nicholas A. (Cupertino CA), Apparatus and method for allocation of resoures in programmable logic devices.
  2. Shail Aditya Gupta ; B. Ramakrishna Rau ; Vinod K. Kathail ; Michael S. Schlansker, Auto design of VLIW processors.
  3. Michael S. Schlansker ; Vinod K. Kathail ; Greg Snider ; Shail Aditya Gupta ; Scott A. Mahlke ; Santosh Abraham, Automated design of processor systems using feedback from internal measurements of candidate systems.
  4. Wang,Albert Ren Rui; Ruddell,Richard; Goodwin,David William; Killian,Earl A.; Bhattacharyya,Nupur; Medina,Marines Puig; Lichtenstein,Walter David; Konas,Pavlos; Srinivasan,Rangarajan; Songer,Christop, Automated processor generation system for designing a configurable processor and method for the same.
  5. Nation,George Wayne; Delp,Gary Scott; Reuland,Paul Gary, Automated selection and placement of memory during design of an integrated circuit.
  6. Colleran, David M.; Hassibi, Arrash, Automatic phase lock loop design using geometric programming.
  7. Oeltjen,Bret Alan; Peterson,Scott Allen; Amundson,Donald Ray; Kirchner,Richard Karl, Automation of the development, testing, and release of a flow framework and methodology to design integrated circuits.
  8. Kunioka Michiko,JPX, Batch execution control programming device and method.
  9. Fattouh, Farag; Abdennadher, Salem, Circuit modeling.
  10. Meiyappan,Subramanian S.; Vajjhala,Varaprasad; Petryk,Edward M., Computer system and method to dynamically generate system on a chip description files and verification information.
  11. Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Mohan Sundararajarao ; Wittig Ralph D., Context-sensitive self implementing modules.
  12. Sharon Sheau-Pyng Lin ; Ping-Sheng Tseng, Converification system and method.
  13. Byrn, Jonathan William; Jensen, James Arnold; Wingren, Matthew Scott, Custom clock interconnects on a standardized silicon platform.
  14. Jain,Jawahar; Narayan,Amit; Kojima,Yoshihisa; Ogawa,Takaya; Iyer,Subramanian K.; Sahoo,Debashis, Determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures.
  15. Abercrombie Andrew P. ; Duncan David A. ; Meeker Woodrow ; Schoomaker Ronald W. ; Van Dyke-Lewis Michele D., Directly accessing local memories of array processors for improved real-time corner turning processing.
  16. Vogel,Danny C., Efficient implementation of multiple clock domain accesses to diffused memories in structured ASICs.
  17. Mohan Sundararajarao ; Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Wittig Ralph D., FPGA modules parameterized by expressions.
  18. Makhlouf, Mahmoud A., Geometric display tools and methods for the visual specification, design automation, and control of adaptive real systems.
  19. Schubert,Nils Endric; McElvain,Kenneth S.; Beardslee,John Mark; Larouche,Mario, Hardware/software co-debugging in a hardware description language.
  20. L. James Hwang ; Eric F. Dellinger ; Sujoy Mitra ; Sundararajarao Mohan ; Cameron D. Patterson ; Ralph D. Wittig, Hetergeneous method for determining module placement in FPGAs.
  21. Hwang L. James ; Dellinger Eric F. ; Mitra Sujoy ; Mohan Sundararajarao ; Patterson Cameron D. ; Wittig Ralph D., Heterogeneous method for determining module placement in FPGAs.
  22. Heimlich Michael C. ; St. Hilaire Kenneth R., Hierarchical adaptive state machine for emulating and augmenting software.
  23. Auracher,Stefan; Pribbernow,Claus; Hils,Andreas, Integrated circuits, and design and manufacture thereof.
  24. Michael D. Rostoker ; Carlos Dangelo ; Daniel R. Watkins, METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULA.
  25. Upton Michael D. (Seattle WA) Rossman Thomas F. (Kirkland WA) Frazier Dean P. (Bellevue WA) Fuller Jay S. (Issaquah WA) Russell Kendall C. (Issaquah WA), Method and apparatus for designing the layout of a subcircuit in an integrated circuit.
  26. Dockser Kenneth A. ; Ehmann Gregory E., Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs.
  27. Baxter, Michael A., Method and apparatus for phase-lock in a field programmable gate array (FPGA).
  28. Schubert, Nils Endric; Beardslee, John Mark; Koch, Gernot Heinrich; Poeppe, Olaf, Method and user interface for debugging an electronic system.
  29. Kochpatcharin Dan ; Sarkari Zarir B. ; Joly Christian ; Wu Allen, Method for creating and using design shells for integrated circuit designs.
  30. Van Huben Gary Alan ; Mueller Joseph Lawrence, Method for managing a plurality of data processes residing in heterogeneous data repositories.
  31. Mohan Sundararajarao ; Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Wittig Ralph D., Method for specifying routing in a logic module by direct module communication.
  32. Park, Jonathan; Chen, Eugen; Saito, Richard; Wright, Adam; Ratchev, Evgueni, Method of creating a mask-programmed logic device from a pre-existing circuit design.
  33. Dai Wei-Jin (Cupertino CA) Galbiati ; III Louis (Mountain View CA) Varghese Joseph (Sunnyvale CA) Bui Dam V. (Milpitas CA) Sample Stephen P. (Mountain View CA), Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a.
  34. Dougherty, W. David, Methodology and graphical user interface for building logic synthesis command scripts using micro-templates.
  35. Mohan,Sunderarajan S., Methodology for design of oscillator delay stage and corresponding applications.
  36. Gary,Scott P.; Cyran,Robert J.; Sarathy,Vijaya B. P., Methodology for managing power consumption in an application.
  37. Wingren, Matthew Scott; Nation, George Wayne; Delp, Gary Scott; Byrn, Jonathan William, Placement of configurable input/output buffer structures during design of integrated circuits.
  38. Kabani,Malik; Lui,Henry, Programmable logic resource with data transfer synchronization.
  39. McClannahan, Gary; Nordman, John Emery; Senst, Scott Thomas; Shaffer, John; Youngman, Todd Jason, Reusable configuration tool.
  40. Broberg, III,Robert Neal Carlton; Byrn,Jonathan William; Delp,Gary Scott; Eneboe,Michael K.; McClannahan,Gary Paul; Nation,George Wayne; Reuland,Paul Gary; Sandoval,Thomas; Wingren,Matthew Scott, Simplified process to design integrated circuits.
  41. Ogami, Kenneth Y.; Zhaksilikov, Marat, Storing of global parameter defaults and using them over two or more design projects.
  42. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul; Mihal, Andrew, System and method for converting graphical programs into hardware implementations which utilize probe insertion.
  43. Poznanovic, Daniel; Hammes, Jeffrey; Krause, Lisa; Steidel, Jon, System and method for partitioning control-dataflow graph representations.
  44. Taylor Brad (Oakland CA) Dowling Robert (Albany CA), System for compiling algorithmic language source code for implementation in programmable hardware.
  45. Lev, Lavi A.; Courtright, David A.; Knowles, John B.; Jones, Darren M., System, method and computer program product for web-based integrated circuit design.
  46. Tiong, Spencer Hao; Lim, Alvin Swee Hock, Systems and methods for generating hardware description code.
  47. Oleksinski,Nicholas A.; Minter,Michael A., Timing constraint generator.

이 특허를 인용한 특허 (1)

  1. Moheban, Lior; Berkovitz, Asher; Shmueli, Guy, Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로