초록 ▼

An obstacle-avoidance-processor chip for three-dimensional path planning comprises an analog processing circuit and at least two analog-resistive-grid networks. The analog processing circuit is communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-d

An obstacle-avoidance-processor chip for three-dimensional path planning comprises an analog processing circuit and at least two analog-resistive-grid networks. The analog processing circuit is communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-detection sensor. The analog processing circuit is configured to construct a three-dimensional obstacle map of an environment based on the received data. The at least two analog-resistive-grid networks are configured to map obstacles in at least two respective non-parallel planes in the constructed three-dimensional obstacle map. The at least two analog-resistive-grid networks form a quasi-three-dimensional representation of the environment. The obstacle-avoidance-processor chip generates information indicative of a three-dimensional unobstructed path in the environment based on the obstacle maps.

대표청구항 ▼

What is claimed is: 1. An obstacle-avoidance-processor chip for three-dimensional path planning, the obstacle-avoidance-processor chip comprising:an analog processing circuit communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-detection sensor, th

What is claimed is: 1. An obstacle-avoidance-processor chip for three-dimensional path planning, the obstacle-avoidance-processor chip comprising:an analog processing circuit communicatively coupled to receive data from an inertial measurement unit and from at least one obstacle-detection sensor, the analog processing circuit configured to construct a three-dimensional obstacle map of an environment based on the received data; andat least two analog-resistive-grid networks, configured to map obstacles in at least two respective non-parallel planes in the constructed three-dimensional obstacle map, and form a quasi-three-dimensional representation of the environment;wherein the obstacle-avoidance-processor chip generates information indicative of a three-dimensional unobstructed path in the environment.