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Graphical user interface with user-selectable list-box

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/177
출원번호 US-0008096 (2001-11-09)
발명자 / 주소
  • Anderson, Doug
출원인 / 주소
  • Cypress Semiconductor Corporation
인용정보 피인용 횟수 : 7  인용 특허 : 1080

초록

A graphical user interface for configuring a programmable integrated circuit is disclosed. More specifically, the graphical user interface may comprise a displayed graphical representation of the programmable integrated circuit, where the graphical representation includes one or more selectable port

대표청구항

What is claimed is: 1. A graphical user interface for configuring a programmable integrated circuit, the graphical user interface comprising:a graphical representation of said programmable integrated circuit displayed on a display device coupled to a computer system, wherein said displayed graphical

이 특허에 인용된 특허 (1080)

  1. Sigfrid Schwarz DE; Gerd Schubert DE; Sven Ring DE; Walter Elger DE; Birgitt Schneider DE; Gunter Kaufmann DE; Lothar Sobek DE, 14,15-cyclopropano steroids of the 19-norandrostane series, method for the production thereof and pharmaceutical preparations containing said compounds.
  2. Yamaki Makio (Tokyo JPX), Accelerated digital signal processor.
  3. Cooper Russell E. (Chandler AZ) Ellison Scott (Chandler AZ), Accurate RC oscillator having peak - to - peak voltage control.
  4. Manlove Gregory Jon (Kokomo IN) Gose Mark Wendell (Kokomo IN), Accurate integrated oscillator circuit.
  5. Wakerly John F. (Mountain View CA), Active cache for a microprocessor.
  6. Mead Carver A. (Pasadena CA) Allen Timothy P. (Palo Alto CA), Adaptable CMOS winner-take all circuit.
  7. Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), Adaptable MOS current mirror.
  8. Mead Carver A. (Pasadena CA) Allen Timothy P. (Palo Alto CA), Adaptable current mirror.
  9. Steinbach Gnter (Sunnyvale CA) Allen Timothy P. (Los Gatos CA) Mead Carver A. (Pasadena CA), Adaptive analog minimum/maximum selector and subtractor circuit.
  10. Philipp Harald (651 Holiday Dr. ; Bldg. 5 ; Suite 300 Pittsburgh PA 15220), Adaptive faucet controller measuring proximity and motion.
  11. Boerstler, David William; Hailu, Eskinder, Adaptive method and apparatus to control loop bandwidth of a phase lock loop.
  12. Canfield Barth A. (Indianapolis IN) Rumreich Mark F. (Indianapolis IN) Schemmann Heinrich (Villingen DEX), Adaptive phase locked loop.
  13. Ruha, Antti; Ruotsalainen, Tarmo; Tervaluoto, Jussi-Pekka; Kauppinen, Jani, Adaptive sigma-delta data converter for mobile terminals.
  14. Hirose Miki,JPX ; Kanoh Kenji,JPX, Amplifier circuit for CMOS operational amplifier.
  15. Gabara Thaddeus John ; Kothandaraman Makeshwar ; Patel Bijit Thakorbhai, Amplifier having improved common mode voltage range.
  16. Goad James R. (Newark CA), Analog input circuit for microcontroller apparatus.
  17. Hyatt Gilbert P. (P.O. Box 81230 Las Vegas NV 89180), Analog memory system having an integrated circuit frequency domain processor.
  18. Swanson, Eric J., Analog to digital conversion circuitry including backup conversion circuitry.
  19. Distinti Robert J. (Fairfield CT), Analog to digital converter.
  20. Lee Robert D. (Austin TX), Analog to digital converter and method of calibrating same.
  21. Signore Bruce D. (Austin TX) Swanson Eric J. (Austin TX), Analog-to-digital converter with a continuously calibrated voltage reference.
  22. Luk찼cs,Istv찼n Endre; Makai,J찼nos; Pfitzner,Lothar; Riesz,Ferenc; Szentpali,B챕la, Apparatus and measurement procedure for the fast, quantitative, non-contact topographic investigation of semiconductor wafers and other mirror like surfaces.
  23. Olgaard Christian, Apparatus and method for a fast locking phase locked loop.
  24. Larson, Lee A.; Swoboda, Gary L.; Hoar, Roland R.; Deao, Douglas E., Apparatus and method for a reconfigurable pod interface for use with an emulator unit.
  25. Schmitz Nicholas A. (Cupertino CA), Apparatus and method for allocation of resoures in programmable logic devices.
  26. Gerpheide George E. ; Griffin Arthur ; Sabbavarapu Anil, Apparatus and method for audible feedback from input device.
  27. Bennett, David W., Apparatus and method for automatically generating circuit designs that meet user output requirements.
  28. Jasa, Hrvoje; Polhemus, Gary D.; Snowdon, Kenneth P., Apparatus and method for calibrating the frequency of a clock and data recovery circuit.
  29. James F. Worley ; Michael J. Blasdel ; Robert R. Hale ; Carolyn A. Lynch, Apparatus and method for controlling secure communications between peripheral components on computer buses connected by a bridge circuit.
  30. Williams Ian Michael, Apparatus and method for dynamic central processing unit clock adjustment.
  31. Dreyer Robert S. (Sunnyvale CA) Alpert Donald B. (Santa Clara CA), Apparatus and method for identifying a computer microprocessor.
  32. Alan L. Herrmann ; Timothy J. Southgate, Apparatus and method for in-system programming of integrated circuits containing programmable elements.
  33. Milburn Blair D., Apparatus and method for initializing a master/checker fault detecting microprocessor.
  34. Takagi, Makoto, Apparatus and method for placing a component.
  35. Stephen L. Wasson, Apparatus and method for programmable datapath arithmetic arrays.
  36. Roohparvar, Frankie F., Apparatus and method for programming voltage protection in a non-volatile memory system.
  37. Keats Dennis ; Xiao Kang, Apparatus and method for providing for efficient communication between high and low-level processing engine of a disk drive formatter.
  38. George E. Gerpheide, Apparatus and method for tactile feedback from input device.
  39. Seymour Edward Michael (Round Rock TX), Apparatus and method for testing a memory array.
  40. Martin San Juan GB, Apparatus and method for testing master logic units within a data processing apparatus.
  41. Thompson Philip Godfrey ; Pilgrim Timothy,IEX, Apparatus and method of powerline surveying, designing in 3D and maintenance.
  42. Shimizu, Akira, Apparatus for and method of measuring capacitance with high accuracy.
  43. Morgan, Mark; Gondi, Srikanth, Apparatus for effecting high speed switching of a communication signal.
  44. Mar Monte F., Apparatus for fast phase-locked loop (PLL) frequency slewing during power on.
  45. Fornek Martin J. (Lisle IL) Kinn Dennis R. (Geneva IL) Meade Steven P. (Bolingbrook IL) Welman Blaine E. (Wheaton IL), Apparatus for interfacing analog telephones and digital data terminals to an ISDN line.
  46. Girardeau ; Jr. James W. (Toulouse FRX), Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor.
  47. Tozun Orhan (Monte Sereno CA) McCune ; Jr. Earl William (Santa Clara CA), Apparatus for reducing jitter of a spectrum spread clock signal and method therefor.
  48. Eldridge,Benjamin N.; Miller,Charles A., Apparatus for reducing power supply noise in an integrated circuit.
  49. McCune ; Jr. Earl W. (2383 Pruneridge Ave. ; Suite 3 Santa Clara CA 95050) Venugopal Narendar (837 Cape Trinity Pl. San Jose CA 95133), Apparatus for spreading the spectrum of a signal and method therefor.
  50. Cheng Vincent (Hsi Chih TWX), Apparatus having dual modes for controlling cursor on display screen.
  51. Nunally Patrick O. ; MacCormack David Ross ; Wilson Charles Park ; Winter Gerhard Josef ; Klein Harry Eric ; Nguyen William Thanh ; Lin-Liu Sen ; Nguyen Lyn ; Auyeung Alex Kamlun ; Pedersen ; Jr. Chr, Apparatus having flexible capabilities for analysis of video information.
  52. Bang, Doo-jin, Apparatus to generate laser beam detect signal.
  53. Chang Web (39939 Stevenson Common ; V-2133 Fremont CA 94538), Application specific field programmable gate array.
  54. Conti, Dennis R.; Lafferty, John, Applying parametric test patterns for high pin count ASICs on low pin count testers.
  55. Getzlaff Klaus J. (Schoenaich DEX) Wille Udo (Holzgerlingen DEX), Arbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiproces.
  56. Ting Benjamin S. (Saratoga CA), Architecture and interconnect scheme for programmable logic circuits.
  57. Snyder, Warren, Architecture for decimation algorithm.
  58. Sullam,Bert, Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocks.
  59. Moore, Michael T., Architecture of a PLL with dynamic frequency control on a PLD.
  60. Worsley Debra J. (Vista CA) Werstlein Michael T. (Sunnyvale CA) Thaik Richard W. (San Jose CA), Asynchronous processor access to a switch table in a network with isochronous capability.
  61. Killian,Earl A.; Gonzalez,Ricardo E.; Dixit,Ashish B.; Lam,Monica; Lichtenstein,Walter D.; Rowen,Christopher; Ruttenberg,John C.; Wilson,Robert P.; Wang,Albert Ren Rui; Maydan,Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
  62. Pope Gregory M. (Santa Cruz CA) Stone Jeffrey F. (Santa Cruz CA) Gregory John A. (Redwood City CA), Automated software testing system.
  63. McCubbrey,David L., Automated system for designing and developing field programmable gate arrays.
  64. Devins, Robert J.; Robinson, James R., Automated system-on-chip integrated circuit design verification system.
  65. Anderson ; II Micheil M. ; Bangerter Howard K. ; Borup Marlon T. ; Byer James E. ; Cable Darin L. ; Doxey Ross W. ; Graham Richard S. ; Hale Todd D. ; Hawley Britt J. ; Lamplugh Richard W. ; Pray Ric, Automated test harness.
  66. Cismas,Sorin C.; Monsen,Kristan J.; So,Henry K., Automatic code generation for integrated circuit design.
  67. Allmond David M. ; Whitmire Laura E. ; Nouri Ahmad ; Hoang Thao Minh ; Hoang Hieu M. ; Bennett Arthur T., Automatic communication protocol detection system and method for network systems.
  68. Allmond David M. ; Whitmire Laura E. ; Nouri Ahmad ; Hoang Thao Minh ; Hoang Hieu M. ; Bennett Arthur T., Automatic communication protocol detection system and method for network systems.
  69. Newhouse Daniel L. (Harrisburg MO) Wheeler Richard G. (Columbia MO) Waltz Ralph H. (Columbia MO), Automatic evaporator system.
  70. Bartz,Manfred; Zhaksilikov,Marat; Roe,Steve; Ogami,Kenneth Y.; Pleis,Matthew A.; Anderson,Douglas H., Automatic generation of application program interfaces, source code, interrupts, and datasheets for microcontroller programming.
  71. Sluiman, Harm; Dougherty, Hetty; Birsan, Dorian, Automatic generation of fastpath applications.
  72. Sharpe-Geisler Bradley A., Band gap reference using a low voltage power supply.
  73. Kutz, Harold; Mar, Monte; Snyder, Warren, Band-gap reference circuit for providing an accurate reference voltage compensated for process state, process variations and temperature.
  74. Junzo Tanaka JP; Masanori Kikuchi JP; Kimihiro Miyamoto JP; Shuji Suwa JP; Shunji Ichikawa JP; Etsuro Yokoyama JP; Soichi Shono JP; Takao Okada JP; Yukari Imamura JP; Kazuo Takakuda JP; Yos, Biological materials.
  75. Ashmore ; Jr. Benjamin Howard ; Marshall Jeffery Mark ; Moyer Bryon Irwin ; Porter John David ; Schmitz Nicholas A. ; Sharpe-Geisler Bradley A., Block clock and initialization circuit for a complex high density PLD.
  76. Jordan Dale A. (20075 SW. Pecan Aloha OR 97006) Fitzsimmons Lynne A. (2905 SW. 107th Portland OR 97225) Greenseth William A. (12255 SW. Foothill Dr. Portland OR 97225) Hoffman Gregory L. (14225 SW. W, Block diagram system and method for controlling electronic instruments with simulated graphic display.
  77. Love Andrew M. (Stafford TX), Bond programmable integrated circuit.
  78. Faggin Frederico (Los Altos Hills CA) Lynch Gary S. (Irvine CA) Sukonick Josef S. (Saratoga CA), Brain emulation circuit with reduced confusion.
  79. Faggin Federico (Los Altos Hills CA) Lynch Gary S. (Irvine CA), Brain learning and recognition emulation circuitry and method of recognizing events.
  80. Platt Alfred, Built-in self test functional system block for UTOPIA interface.
  81. Mozingo Kenneth D. (Yorkville IL) Stroud Charles E. (North Aurora IL), Built-in self-test (BIST) circuit.
  82. Daniel W. Green, Built-in self-test circuit and method for validating an associative data array.
  83. May, Roger; Tyson, James; Flaherty, Edward; Dickinson, Mark, Bus architecture for system on a chip.
  84. Gamal Abbas El ; Marple David P. ; Reyneri Justin M., CAD and simulation system for targeting IC designs to multiple fabrication processes.
  85. Lin Jonathan (Milpitas CA) Peng Jack Z. (San Jose CA) Barsan Radu (Cupertino CA) Mehta Sunil (San Jose CA), CMOS EEPROM cell with tunneling window in the read path.
  86. Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), CMOS amplifier with offset adaptation.
  87. Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA), CMOS amplifier with offset adaptation.
  88. Mead Carver A. (Pasadena CA) Allen Timothy P. (Palo Alto CA), CMOS amplifier with offset adaptation.
  89. Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), CMOS current mirror with offset adaptation.
  90. Sharpe-Geisler Bradley A. (San Jose CA) Lin Jonathan (Milpitas CA) Barsan Radu (Cupertino CA), CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separatin.
  91. Hanke Carl C. (Mesa AZ) Obregon Carlos D. (Tempe AZ) Sutton Timothy W. (Mesa AZ), CMOS power-on reset circuit.
  92. Weber, David J.; Yue, Patrick; Su, David, CMOS transceiver having an integrated power amplifier.
  93. Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA) Allen Timothy P. (Los Gatos CA) Wall Michael F. (Sunnyvale CA), CMOS winner-take all circuit with offset adaptation.
  94. Takeda Koji (Suwa JPX), CPU clock generator having a low frequency output during I/O operations and a high frequency output during memory operat.
  95. Gehring, Mark Richard; Jensen, Brent R., Calibration of integrated circuit time constants.
  96. Kitano,Mayo; Sumi,Hideki; Moribe,Tsuyoshi, Capacitance difference detecting circuit and MEMS sensor.
  97. Lund, John M.; Eng, Jr., Benjamin, Capacitance measurement.
  98. Snyder,Warren S.; Ess,David Van, Capacitance sensor using relaxation oscillators.
  99. Gerpheide George E. (Salt Lake City UT) Layton Michael D. (Salt Lake City UT), Capacitance-based proximity with interference rejection apparatus and methods.
  100. Harald Philipp GB, Capacitive closure obstruction sensor.
  101. Shaw, Scott J.; Day, Shawn P.; Trent, Jr., Raymond A.; Gillespie, David W.; Errington, Andrew M., Capacitive mouse.
  102. Shaw,Scott J.; Day,Shawn P.; Trent, Jr.,Raymond A.; Gillespie,David W.; Errington,Andrew M., Capacitive mouse.
  103. Schediwy, Richard; Huie, Mark; Cook, Charles, Capacitive pointing stick.
  104. Philipp Harald, Capacitive position sensor.
  105. Philipp, Harald, Capacitive position sensor.
  106. Hourmand Byron, Capacitive responsive electronic switching circuit.
  107. Casebolt, Mark W.; Rensberger, Gary; Bathiche, Steven N.; Abulet, Mihai, Capacitive sensing and data input device power management.
  108. Harald Philipp GB, Capacitive sensor and array.
  109. Howard,Jack E.; Lieder,Oliver H.; Bowlds,Brian Burket; Lindsay,Paul Austin, Capacitive sensor and method for non-contacting gap and dielectric medium measurement.
  110. Philipp Harald (651 Holiday Dr. ; Bldg 5 ; Ste. 300 Pittsburgh PA 15200), Capacitively coupled identity verification and escort memory apparatus.
  111. Nishi, Masahiro, Capacitor and method for fabricating the same.
  112. Todsen James L. ; Kalthoff Timothy V., Capacitor array having user-adjustable, manufacturer-trimmable capacitance and method.
  113. Snyder,Warren, Capturing test/emulation and enabling real-time debugging using an FPGA for in-circuit emulation.
  114. Bien David E., Cascode single-ended to differential converter.
  115. Preuss, Curtis Walter; Hanson, Charles C., Center tap level control for current mode differential driver.
  116. Azegami Kengo,JPX ; Yamashita Koichi,JPX, Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time.
  117. Puccio, Gianni; Bisanti, Biagio; Cipriani, Stefano, Charge pump phase locked loop with improved power supply rejection.
  118. Harald Philipp GB, Charge transfer capacitance measurement circuit.
  119. Weed,Dan, Chip management system.
  120. Gong,Jung Chul; Kwon,Kyoung Soo; Hwang,Hyeon Seok; Kim,Sang Suk, Circuit and method for compensating for offset voltage.
  121. Sha, I-Teh; Chen, Kuang-Yu; Chen, Albert, Circuit and method for controlling a spread spectrum transition.
  122. Abugharbieh Khaldoon ; Min Sung-Ki, Circuit and method for controlling an output of a ring oscillator.
  123. Sha, I-Teh; Chen, Albert; Chen, Kuang-Yu, Circuit and method for linear control of a spread spectrum transition.
  124. Sen-Jung Wei ; Kuang-Yu Chen, Circuit and method for preventing runaway in a phase lock loop.
  125. Anderson David J. (Scottsdale AZ), Circuit and method of canceling leakage current in an analog array.
  126. Parker Lanny L. (Mesa AZ) Atriss Ahmad H. (Chandler AZ) Mueller Dean W. (Portland OR), Circuit and method of switching between redundant clocks for a phase lock loop.
  127. Jens Grunert DE, Circuit arrangement for in-circuit emulation of a microcontroller.
  128. Schutte Herman (Eindhoven NLX), Circuit comprising a data communication bus.
  129. Takahashi Hiromichi (Tokyo JPX), Circuit emulator.
  130. Kasperkovitz, Wolfdietrich Georg, Circuit for measuring absolute spread in capacitors implemented in planary technology.
  131. Kowalczyk Robert M. (Chandler AZ) Brown ; III Robert H. (Chandler AZ) Heller Jack W. (Mesa AZ), Circuit for sharing a memory of a microcontroller with an external device.
  132. Viehmann, Hans-Heinrich; Lammers, Stefan, Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption.
  133. Dathe, Lutz; Drescher, Henry, Circuit for tuning an active filter.
  134. Satish C. Saripella, Circuit technique for improved current matching in charge pump PLLS.
  135. Mar Monte F., Circuit(s), architecture and method(s) for operating and/or tuning a ring oscillator.
  136. Pawloski Martin B. (Gilbert AZ), Circuitry for producing emulation mode in single chip microcomputer.
  137. Ranson Gregory L. ; Bockhaus John W. ; Lesartre Gregg B. ; Knebel Patrick ; Perez Paul L., Circuitry for providing external access to signals that are internal to an integrated circuit chip package.
  138. McDonald, II, James J.; Hulfachor, Ronald B., Circuitry to reduce PLL lock acquisition time.
  139. Son, Young-Jae; Cho, Uk-Rae; Lee, Kwang-Jin, Circuits and methods for screening for defective memory cells in semiconductor memory devices.
  140. Platt John C. (Mountain View CA) Wall Michael F. (Sunnyvale CA) Gribble Glenn E. (San Jose CA) Mead Carver A. (Pasadena CA), Circuits for linear conversion between currents and voltages.
  141. Platt John C. (Mountain View CA) Wall Michael F. (Sonnyvale CA) Gribble Glenn E. (San Jose CA) Mead Carver A. (Pasadena CA), Circuits for linear conversion between voltages and currents.
  142. Kapusta Richard L. ; Marshall Jeffery Mark ; Mohammed Haneef D., Circular product term allocations scheme for a programmable device.
  143. Kekic, Miodrag M.; Lu, Grace N.; Carlton, Eloise H., Client-server computer network management architecture.
  144. McDonald, Duncan R.; Herndon, Matthew, Client-server simulator, such as an electrical circuit simulator provided by a web server over the internet.
  145. Dalmia Kamal, Clock and data recovery PLL based on parallel architecture.
  146. Biesterfeldt Randall P. (Austin TX), Clock control system for microprocessors including a delay sensing circuit.
  147. Korhonen Sirpa (Ravattula FIX) Lindholm Rune (Salo FIX), Clock frequency adjustment of an electrical circuit.
  148. Akiyama Shin-ichiro (Tokyo JPX), Clock generating circuit for use in single chip microcomputer.
  149. Douezy, Francois; Reblewski, Frederic; Barbier, Jean, Clock generation and distribution in an emulation system.
  150. Kohara, Ryuichi, Clock supply circuit.
  151. Eto Satoshi,JPX ; Nakamura Toshikazu,JPX, Clock supplying circuit and integrated circuit device using it.
  152. MacGregor William W. (Wellesley MA), Clock system having adaptive synchronization feature.
  153. Camilleri, Nicolas J.; McGettigan, Edward S.; Stickney, Jr., Kenneth J.; Lindholm, Jeffrey V.; Bixler, Kevin L.; Kong, Raymond, Clock template for configuring a programmable gate array.
  154. Trent, Jr.,Raymond A.; Shaw,Scott J.; Gillespie,David W.; Heiny,Christopher; Huie,Mark A., Closed-loop sensor on a solid-state object position detector.
  155. Matyas Stephen M. (Kingston NY) Oseas Jonathan (Hurley NY), Code protection using cryptography.
  156. Fernandes Antonio M., Collaboration centric document processing environment using an information centric visual user interface and information presentation method.
  157. Nemecek,Craig; Roe,Steve, Combined in-circuit emulator and programmer.
  158. Bloom, Andrew Maurice; Escoto, Rodrigo Jose, Combined waveform and data entry apparatus and method for facilitating fast behavioral verification of digital hardware designs.
  159. Hrassky Petr (Wasserburg DEX), Comparator with extended common-mode input voltage range.
  160. Liu,Zhongding; Bi,Joe; Li,Ken Ming; Pan,Gray; Yang,Gary, Comparators capable of output offset calibration.
  161. Quintus John J. (Buena Park CA) Sheehan Michael S. (Santa Ana CA), Compensation circuit for nullifying differential offset voltage and regulating common mode voltage of differential signa.
  162. John M. Washeleski ; Randall L. Perrin, Compressible capacitance sensor for determining the presence of an object.
  163. Burckhartt David M. ; Perez Lazaro D. ; Emerson Theodore F. ; Dow Randolph O. ; Stimac Gary A., Computer failure recovery and alert system.
  164. LaGrange George W. ; Gerpheide George E. ; Woolley Richard D. ; Donohue Tom ; Layton Mike, Computer input stylus method and apparatus.
  165. Beasley Danny L. ; Seifert ; Jr. Robert V. ; Lacrampe Paul ; Huffington James C. ; Greene Thomas ; Hafer Kevin J., Computer interconnection system having analog overlay for remote control of the interconnection switch.
  166. Casselman Steven M., Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed.
  167. Meiyappan,Subramanian S.; Vajjhala,Varaprasad; Petryk,Edward M., Computer system and method to dynamically generate system on a chip description files and verification information.
  168. Jeddeloh Joseph, Computer system with a switch interconnector for computer devices.
  169. Lawman Gary R. (San Jose CA) Wells Robert W. (Cupertino CA), Concurrent electronic circuit design and implementation.
  170. Grucci, Kyle T.; Vellayappan, Raman; Frechette, Arthur D.; Frechette, Alan E., Concurrent execution and logging of a component test in an enterprise computer system.
  171. Tzori Yiftach, Concurrent hardware-software co-simulation.
  172. Hosticka Bedrich (Duisburg DEX) Schardein Werner (Kamp-Lintfort DEX) Weghaus Berthold (Dinslaken DEX), Configurable analog and digital array.
  173. Brian C. Faith ; Thomas Oelsner GB; Gary N. Lai, Configurable computational unit embedded in a programmable device.
  174. Snyder, Warren, Configurable input/output interface for a microcontroller.
  175. Bernard J. New ; Ralph D. Wittig ; Sundararajarao Mohan, Configurable logic element with expander structures.
  176. Landry Greg J., Configurable memory block.
  177. Lacey, Timothy M.; Johnson, David L., Configurable memory for programmable logic circuits.
  178. Timothy M. Lacey ; David L. Johnson, Configurable memory for programmable logic circuits.
  179. Darmawaskita, Hartono; Eagar, Layton, Configurable operational amplifier as a microcontroller peripheral.
  180. Rangasayee Krishna, Configuration eprom with programmable logic.
  181. Couts-Martin Chris ; Herrmann Alan, Configuration memory integrated circuit.
  182. Snyder, Warren, Configuring digital functions in a digital configurable macro architecture.
  183. Paul Glad, Connector and support system for a touchpad keyboard for use with portable electronic appliances.
  184. Konkle, Timothy A., Constraint-based language configuration files for updating and verifying system constraints.
  185. Frederiksen, Steen Lillethorup, Context sensitive pop-up window for a portable phone.
  186. Mead Carver A. (Pasadena CA) Anderson Janeen D. W. (Fremont CA) Platt John C. (Mountain View CA), Continuous synaptic weight update mechanism.
  187. Gorecki James L. (Hillsboro OR), Continuous time programmable analog block architecture.
  188. King Ken Richard ; Fischer Mark Charles, Control circuit having multiple functions set by a single programmable terminal.
  189. King Ken Richard, Control circuit with both positive and negative sensing.
  190. Ekstedt Thomas W. (Palo Alto CA) Dryden Mary L. (Mountain View CA) Kaempf Ulrich (Los Altos CA) Clark Richard R. (Redwood City CA), Control system for automated parametric test equipment.
  191. Caldwell, David W., Control system input apparatus and method.
  192. White, Jason, Creating a graphical program to configure one or more switch devices.
  193. Curtis, Bryce Allen, Cross platform program installation on drives using drive object.
  194. Fernald, Kenneth W.; Alfano, Donald E., Cross-bar matrix for connecting digital resources to I/O pins of an integrated circuit.
  195. Albert Mu ; Jeffrey D. Larson, Crossbar switch and method with crosspoint circuit.
  196. Sutardja,Sehat, Crystal oscillator emulator.
  197. Collins Timothy ; Pucci Gregory, Crystal oscillator having input/output pins selectively used for analog or digital signals.
  198. Mar, Monte; Snyder, Warren, Crystal-less oscillator circuit with trimmable analog current control for increased stability.
  199. Stiff, Jonathon C., Current controlled delay circuit.
  200. Dening, David, DC-DC converter with reduced electromagnetic interference.
  201. Hawkes Charles E., DC-to-DC converter having charge pump and associated methods.
  202. Belhaj, Said O., DSP emulating a microcontroller.
  203. Bartz, Manfred; Zhaksilikov, Marat; Ogami, Kenneth Y., Data driven method and system for monitoring hardware resource usage for programming an electronic device.
  204. Seiji Hamada JP; Robert Logie JP; Takashi Ogura JP, Data item display method and device, and recording medium storing a program for controlling display of data item.
  205. Kitagaki Takashi,JPX, Data processing apparatus for IC tester.
  206. Hohl William A. ; Circello Joseph C., Data processing system for controlling execution of a debug function and method thereof.
  207. Circello Joseph C. ; Riedel Klaus R., Data processing system for performing a trace function and method therefor.
  208. Moughanni Claude ; Moyer William C. ; Aslam Taimur, Data processor with a privileged state firewall and method therefore.
  209. Scott Paul H., Data recovery phase locked loop.
  210. Greeff, Roy; Ovard, David; Lee, Terry R., Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection.
  211. Bartz, Manfred; Zhaksilikov, Marat, Datasheet browsing and creation with data-driven datasheet tabs within a microcontroller design tool.
  212. Held James P., Debugger for debugging tasks in an operating system virtual device driver.
  213. Nishibata Motohide,JPX ; Iwamura Yoshiyuki,JPX ; Sumi Fumio,JPX, Debugging apparatus for debugging a program by changing hardware environments without changing program operation state.
  214. Katsuhiko Ueki JP, Debugging support device and debugging support method.
  215. Waizman Alexander (Haifa ILX), Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle.
  216. Zaidi,S. Jauher A.; Ou,Michael; Adams,Lyle E.; Chappell,Stephen; Gandikota,Savitha; Udell,Jon; Gutcher,Brian; Munsil,Jef, Design tool for systems-on-a-chip.
  217. Gramegna,Giuseppe, Device for calibrating the frequency of an oscillator, phase looked loop circuit comprising said calibration device and related frequency calibration method.
  218. Miyazawa, Naoyuki, Device having interdigital capacitor.
  219. Tice Thomas E. (Greensboro NC) Crook David T. (Summerfield NC) Kattmann Kevin M. (Greensboro NC) Lane Charles D. (Greensboro all of NC), Differential amplifiers which can form a residue amplifier in sub-ranging A/D converters.
  220. Itakura Tetsuro (Kanagawa JPX), Differential input circuit and operational amplifier with wide common mode input voltage range.
  221. Bonaccio Anthony R. (Shelburne VT) Gersbach John E. (Burlington VT), Differential receiver with high common-mode range.
  222. Main William E. (Mesa AZ), Differential relaxation oscillator.
  223. Proebsting Robert J., Differential sense amplifier circuit.
  224. Belot Didier,FRX ; Dugoujon Laurent,FRX, Differential stage logic circuit.
  225. Metz Arthur J. (Gervais OR), Differential to single-ended converter.
  226. Tran Toan (San Jose CA), Differential to single-ended converter.
  227. Jarrett Robert B. (Tempe AZ) Pace Wilson D. (Tempe AZ), Differential to single-ended converter utilizing inverted transistors.
  228. M?ller, David; Rebmann, Volkmar, Differential to single-ended logic converter.
  229. Caldwell David W., Differential touch sensor and control circuit therefor.
  230. LaRosa Christopher Peter (Lake Zurich IL) Carney Michael John (Mundelein IL), Digital FM demodulator.
  231. Timo Gossmann DE; Edmund Gotz DE, Digital PLL (phase-locked loop) frequency synthesizer.
  232. Perrott Michael H. ; Sodini Charles G. ; Chandrakasan Anantha P., Digital compensation for wideband modulation of a phase locked loop frequency synthesizer.
  233. Snyder, Warren, Digital configurable macro architecture.
  234. Snyder, Warren, Digital configurable macro architecture.
  235. Jordan Thomas Harmon, Digital control system and method for generator sets.
  236. Dent Paul W., Digital frequency synthesis by sequential fraction approximations.
  237. Tzori Yifatch, Digital logic simulation/emulation system.
  238. Lo Chung-Wen Dennis, Digital phase detector and charge pump system reset and balanced current source matching.
  239. Tran Toan V. (San Jose CA) Henderson Richard (Sunnyvale CA), Digital phase lock loop having frequency offset cancellation circuitry.
  240. Dalmia, Kamal, Digital phase/frequency detector, and clock generator and data recovery PLL containing the same.
  241. Paul F. Beard ; Mark D. Moore ; Drew M. Harrington, Digital radiofrequency transceiver.
  242. Okuaki Yasuyuki (Tokyo JPX) Yamamoto Kazushige (Tokyo JPX), Digital signal processor evaluation chip and debug method.
  243. Beard,Paul, Digital signal processor transceiver.
  244. Seguine Dennis R. ; Stice John R. ; LaBrash Stephen P., Digital sliding pole fast-restore for an electrocardiograph display.
  245. Rempfer William C. (San Jose CA), Digital to analog converter.
  246. Smith Michael D. (Lewisville TX), Digital to analog converter using a programmable logic array.
  247. Brokaw Adrian Paul (Burlington MA), Digital-to-analog converter with current source transistors operated accurately at different current densities.
  248. Moody Kristaan L. (Nottingham NH) Latham ; II Paul W. (Lee NH), Digitally dual-programmable integrator circuit.
  249. O\Shaughnessy Timothy G. (Black Forest CO), Digitally-tuned oscillator including a self-calibrating RC oscillator circuit.
  250. Aslan Mehmet ; Can Sumer, Direct temperature sensing of a semiconductor device semiconductor device.
  251. Cloke Robert L. ; Hull Richard W. ; Rakshani Vafa James ; Turner David P., Disk drive employing read channel IC with common port for data and servo.
  252. Gaston, Michael T.; Cook, David; Gandhi, Goutam; Hedrick, Gary D.; Potter, Victor L.; Lecheler, Carl J.; Matt, Timothy S., Distributed life cycle development tool for controls.
  253. Wang, David Y.; Cheng, Yu-Chi, Divide-by-N differential phase interpolator.
  254. Philipp Harald (4812 Scott Rd. Lutz FL 33549), Divided box for valve controller.
  255. Gorecki, James L.; Gazeley, Bill G.; Yang, Yaohua, Double differential comparator and programmable analog block architecture using same.
  256. John M. Callahan, Dual die memory.
  257. Shutt,James, Dual mode relaxation oscillator generating a clock signal operating at a frequency substantially same in both first and second power modes.
  258. Aimoto Yoshiharu (Tokyo JPX) Sugibayashi Tadahiko (Tokyo JPX), Dual port memory having a plurality of memory cell arrays for a high-speed operation.
  259. Huang Hung-Ta (Taipei TWX), Dual socket upgradeable computer motherboard with automatic detection and enablement of inserted upgrade CPU chip.
  260. Smith Lewis R. (Tucson AZ) Thomas David M. (Tucson AZ), Dummy/trim DAC for capacitor digital-to-analog converter.
  261. Ward Dennis R., Durable bowstring and buss cable.
  262. Parmenter Kevin C. (Carrollton TX) Takahashi Yutaka (Dallas TX), Dynamic clock mode switch.
  263. Hirsch Peter Douglas, Dynamic object visualization and code generation.
  264. Kung, Shao-Tsu; Cheng, Chih-Chuan; Liu, Chun-Chih; Chen, Yi-Chang, Dynamic power saving by monitoring CPU utilization.
  265. Pleis,Matthew A.; Ogami,Kenneth Y., Dynamic reconfiguration interrupt system and method.
  266. Pontarelli Mark C. (P.O. Box 160097 Cupertino CA 95016-0097), Dynamic speed switching software for power management.
  267. Mead Carver A. (Pasadena CA) Allen Timothy P. (Palo Alto CA) Faggin Federico (Los Altos Hills CA), Dynamic synapse for neural network.
  268. Qureshi, Qadeer A.; Davar, Sushama; Jew, Thomas, Dynamic voltage adjustment for memory.
  269. Parrish, Sean T., Dynamically controlling a power state of a graphics adapter.
  270. Kwiat Kevin Anthony, Dynamically reconfigurable FPGA apparatus and method for multiprocessing and fault tolerance.
  271. Collins Arthur A. (Dallas TX), Dynamically reconfigurable time-space-time digital switch and network.
  272. Wang, Sheng Hung; Kim, Simon S., Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses.
  273. Gerpheide, George, Efficient entry of characters from a large character set into a portable information appliance.
  274. Thomas C. Bowen, Electric continuously variable transmission.
  275. Gerpheide George E. (Salt Lake City UT), Electrical charge transfer apparatus.
  276. Allen Timothy P. (Los Gatos CA) Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA), Electrically adaptable neural network with post-processing circuitry.
  277. Faggin Federico ; Seely Joel A. ; Allen Timothy P., Electronic device employing a touch sensitive transducer.
  278. Steenwyk,Timothy Edward, Electronic door latch system with water rejection filtering.
  279. Billings Zeb (Hartland WI), Electronic musical instrument with sound-control panel and keyboard.
  280. Bhandari Narpat (Los Gatos CA) Watkins Daniel R. (Saratoga CA), Electronic simulation and emulation system.
  281. Veenstra Kerry S., Embedded memory block with FIFO mode for programmable logic device.
  282. Swoboda Gary L. ; Ing-Simmons Nicholas K.,GB2 ; Simpson Richard David,GB2, Emulation devices, systems, and methods.
  283. Yamaura Shinichi (Kobe JPX) Yoshioka Keiichi (Sanda JPX) Hara Kazuhiko (Ikeda JPX) Katayama Takao (Ikeda JPX), Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core.
  284. Snyder,Warren; Nemecek,Craig; Sullam,Bert, Emulator chip/board architecture and interface.
  285. Stansell Galen E., Enabling clock signals with a phase locked loop (PLL) lock detect circuit.
  286. Herczeg Karen L. (Rochester NY) McVay David M. (Rochester NY), End pulse width modulation for digital image printer with halftone gray scale capability.
  287. Philipp Harald (15320 NE. 11th ; K326 Bellevue WA 98007), Energy field sensor using summing means.
  288. Veenstra, Kerry; Rangasayee, Krishna; Herrmann, Alan L., Enhanced embedded logic analyzer.
  289. Duboc, Jean Francois; Oddoart, Romain, Enhanced programmable core model with integrated graphical debugging functionality.
  290. Lutz, Donald G.; Duggan, Daniel, Environmental monitoring system.
  291. Mann Eric N. (Issaquah WA) Torode John Q. (Hunts Point WA), Erasable and programmable single chip clock generator.
  292. Beauvais David L., Error recovery system for an energy controller for an electric water heater.
  293. Stoica, Adrian; Salazar-Lazaro, Carlos Harold, Evolutionary technique for automated synthesis of electronic circuits.
  294. Yalcinalp, L. Umit, Extending the capabilities of an XSL style sheet to include components for content transformation.
  295. Young Steven P., FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines.
  296. Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals.
  297. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.
  298. Sasaki Paul Takao ; Vora Madhukar ; West Burnell G, FPGA with conductors segmented by active repeaters.
  299. Pope Kevin (Poway CA) Hartmann Paul R. (Escondido CA), Facilities data link handler in a performance monitoring and test system.
  300. Mann, Eric N.; Wunner, John J., Fail-safe zero delay buffer with automatic internal reference.
  301. Pradhan, Pravas, Failsafe differential amplifier circuit.
  302. Maddy Steven L. (Boulder CO) Paterson Graeme S. (Boulder CO), Fast settling phase locked loop.
  303. Leung Wingyu (Cupertino CA) Hsu Fu-Chieh (Saratoga CA), Fault-tolerant hierarchical bus system and method of operating same.
  304. Gilson Kent L. (Salt Lake City UT), Fault-tolerant waferscale integrated circuit device and method.
  305. Philipp Harald (4885A McKnight Rd. #283 Pittsburgh PA 15237), Fiber optic security system.
  306. Steenwyk,Timothy Edward, Field effect sensor two wire interconnect method and apparatus.
  307. Barnett Philip C.,GBX, Field programmable gate array (FPGA) emulator for debugging software.
  308. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells.
  309. New Bernard J., Field programmable gate array with dedicated computer bus interface and method for configuring both.
  310. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array with distributed RAM and increased cell utilization.
  311. Paulsen Mark T. (Chanhassen MN) Tonkin Steven W. (Eden Prairie MN), Field-programmable electronic crossbar system and method for using same.
  312. Grider Stephen N. (Farmers Branch TX), Filtered detection plus propagated timing window for stabilizing the switch from crystal to ring oscillator at power-dow.
  313. Gillig Steven F. (Roselle IL) Hietala Alexander W. (Cary IL), Filtering device for use in a phase locked loop controller.
  314. Kiriaki Sami ; Krenik William R., Fir filter architecture.
  315. Tobita Tsunehiro (Yokohama JPX) Kitahara Jun (Yokohama JPX) Tsunehiro Takashi (Ebina JPX) Katayama Kunihiro (Yokohama JPX) Hattori Ryuichi (Kawasaki JPX) Seki Yukihiro (Yokohama JPX) Yamagami Hajime , Flash memory control method and information processing system therewith.
  316. Chang, Chao-I; Zhang, Ji Yun, Flash memory controller with updateable microcode.
  317. Lee, Jong Soo, Flash memory device employing disturbance monitoring scheme.
  318. Ahanin Bahram (Cupertino CA) Balicki Janusz K. (San Jose CA) Kiani Khusrow (Oakland CA) Leong William (San Francisco CA) Li Ken-Ming (Santa Clara CA) Nouban Bezhad (Fremont CA), Flexible configuration logic array block for programmable logic devices.
  319. Gerpheide, George; Taylor, Brian; Woolley, Richard; Lee, Daniel, Flexible touchpad sensor grid for conforming to arcuate surfaces.
  320. Brady,Philomena Cleopha; Lo,Haw Jing; Serrano,Guillermo Jos챕; Adil,Farhan; Kucic,Matthew Raymond; Hasler,Paul Edward; Anderson,David V.; Pereira,Angelo W., Floating-gate reference circuit.
  321. Bierenbaum, Steven E., Flow designer for establishing and maintaining assignment and strategy process maps.
  322. Frisch Josef C. ; Leyh Gregory E. ; Platt John C. ; Allen Timothy P. ; Schediwy Richard R. ; Faggin Federico, Force sensing touchpad.
  323. Thomson, David; Blake, John; Manus, Lorcan Mac, Four current transistor temperature sensor and method.
  324. Moyal, Nathan Y.; Williams, Bertrand J.; Marlett, Mark; Meyers, Steve, Frequency acquisition rate control in phase lock loop circuits.
  325. Shutt,James; Kutz,Harold, Frequency doubler circuit with trimmable current control.
  326. Klemmer Nikolaus, Frequency doubling circuits, method, and systems including quadrature phase generators.
  327. Motoyoshi, Toshiro; Nagata, Kimihiko, Frequency synthesizer circuit.
  328. Tarusawa Yoshiaki (Yokohama JPX) Saito Shigeki (Yokohama JPX) Yamao Yasushi (Yokosuka JPX) Nojima Toshio (Yokosuka JPX), Frequency synthesizer having compensation for nonlinearities.
  329. Mohan Jitendra, Fully switched, class-B, high speed current amplifier driver.
  330. Alexander, Jay A., Generation and execution of instrument control macro files for controlling a signal measurement system.
  331. Southgate Timothy J. ; Wenzler Michael, Graphic editor for block diagram level design of circuits.
  332. Southgate, Timothy J.; Wenzler, Michael, Graphic editor for block diagram level design of circuits.
  333. McDonald Ryan O. ; Kudukoli Ramprasad ; Richardson Gregory C., Graphical code generation wizard for automatically creating graphical programs.
  334. Thomsen Carsten ; Kodosky Jeffrey L., Graphical programming system and method including three-dimensional nodes with pre-defined input and output capabilities.
  335. Kodosky Jeffrey L. ; Truchard James J. ; MacCrisken John E., Graphical system for modelling a process and associated method.
  336. Fang, Chi, Graphical user interface including hyperlinks in a help message dialog box.
  337. Muratori, Richard D.; Wilde, Myles J.; Hooper, Donald F., Graphical user interface that displays operation of processor threads over time.
  338. Hong,Jerry, Graphical user interface with enhanced operations when changing display screen.
  339. Anderson,Douglas; Roe,Steven; Nemecek,Craig, Graphical user interface with logic unifying functions.
  340. Lawman Gary R., HDL design entry with annotated timing.
  341. Philipp Harald, Hammer having integral stud and mains sensor.
  342. Takeshi Suzuki JP, Hand mechanism of library apparatus comprising integrated rotatable plate portion and bar code reader.
  343. Platt John C. ; Nowlan Steven ; Decker Joseph ; Matic Nada, Handwriting recognition system and method.
  344. Daynes, John C.; Marquardt, Judith F.; Sequine, Dennis R., Hard paddle for an external defibrillator.
  345. Hellestrand Graham R. ; Cheung King Yin,HKX ; Torossian James R.,AUX ; Chan Ricky L. K.,AUX ; Kam Ming Chi,AUX ; Yong Foo Ngok,AUX, Hardware and software co-simulation including simulating the cache of a target processor.
  346. Brian Bailey, Hardware and software co-verification employing deferred synchronization.
  347. Schubert, Nils Endric; Beardslee, John Mark; Perry, Douglas L., Hardware debugging in a hardware description language.
  348. Lopez Ted J. ; Jones Scott A. ; Laffey Thomas M., Hardware-assisted firmware tracing method and apparatus.
  349. Betz, Vaughn; Rose, Jonathan, Heterogeneous interconnection architecture for programmable logic devices.
  350. Mori Masakazu (Kawasaki JPX) Fukushima Takeo (Kawasaki JPX) Fujimoto Naonobu (Kawasaki JPX), Hierarchical data transmission system.
  351. Moore Wesley (Morrisville NC) Huffman Ward (Durham NC), Hierarchical floorplanner for gate array design layout.
  352. Ho Walford W. (Saratoga CA) Chen Chao-Chiang (Cupertino CA) Yang Yuk Y. (Foster City CA), Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array.
  353. Lee I-Shi (Taipei TWX) Shen Tim H. T. (Tao-Yuan TWX) Huang Stephen R. M. (Hsin Chu TWX) Kuo Judy C. L. (Hsin Chu TWX), High frequency clock generator with multiplexer.
  354. Charles N. Choukalos ; Alvar Antonio Dean ; Scott Alan Tetreault ; Sebastian Theodore Ventrone, High level automatic core configuration.
  355. Bailey, Jay Patrick; Copley, Brian J.; Freitas, Mark J., High performance communications interface.
  356. Gustavsson, Mikael; Tan, Nianxiong, High performance switched-capacitor filter for oversampling Sigma-Delta digital to analog converters.
  357. Tedrow Kerry D. (Orangevale CA) Keeney Stephen N. (Sunnyvale CA) Fazio Albert (Los Gatos CA) Atwood Gregory E. (San Jose CA) Javanifard Johnny (Sacramento CA) Woiciechowski Kenneth (Folsom CA), High precision voltage regulation circuit for programming multilevel flash memory.
  358. Stanley,Michael E., High resolution pulse width modulator.
  359. Burlison Phillip D. (Morgan Hill CA) DeHaven William R. (Los Altos CA) Pogrebinsky Victor (San Jose CA), High speed IDDQ monitor circuit.
  360. Chan Eric, High speed asynchronous digital testing module.
  361. John P. Mullaney ; Gary M. Lee, High speed cross point switch routing circuit with word-synchronous serial back plane.
  362. Phillips, Michael D.; Wilburn, Darrell L.; Hua, Van T.; Minami, Gordon A.; Kresge, Robert J.; Verhaegh, Charles, High speed microcomputer in-circuit emulator.
  363. Seltzer Jeffrey H. (Los Gatos CA) Jenkins ; IV Jesse H. (Danville CA) Diba Sholeh (Los Gatos CA), High speed product term allocation structure supporting logic iteration after committing device pin locations.
  364. Mead Carver A. (Pasadena CA), High-density photosensor and contactless imaging array having wide dynamic range.
  365. Walden Robert H. (Newbury Park CA) Temes Gabor C. (Los Angeles CA) Cataltepe Tanju (Red Bank NJ), High-order sigma-delta analog-to-digital converter.
  366. Chen, Yi-Huei; Huang, Po-Chiun, High-speed differential to single-ended converter.
  367. Ling, Kuok, High-speed fully balanced differential flip-flop with reset.
  368. Hatano, Hideki; Yamaji, Takashi; Kitamura, Kenji; Takekawa, Shunji; Nakamura, Masaru, Holographic recording medium and holographic recording/reproducing apparatus using the same.
  369. Nemecek,Craig, Host to FPGA interface in an in-circuit emulation system.
  370. Moody Kristaan L. (Nottingham NH) Latham ; II Paul W. (Lee NH), Hybrid control law servo co-processor integrated circuit.
  371. Hirsch Peter Douglas, Hyperlinked relational database visualization system.
  372. McClintock Cameron ; Cliff Richard G. ; Wang Bonnie I., I/O cell configuration for multiple I/O standards.
  373. Dijkmans Eise C. (Eindhoven NLX) Graffenberger Wilhelm (Hamburg DEX) Kilian Ernst A. (Hamburg DEX), I2L gate circuit arrangement having a switchable current source.
  374. Koyama Jo,JPX, IC testing apparatus.
  375. Piasecki, Douglas S.; Storvik, II, Alvin C., IC with digital and analog circuits and mixed signal I/O pins.
  376. Joseph E. Decker, Identity verification methods.
  377. Ooshita, Takeshi, Impedance control circuit for controlling multiple different impedances with single control circuit.
  378. Pawloski, Martin B, In-circuit emulation of single chip microcontrollers.
  379. Suzuki Noriyuki (Tokyo JPX) Asai Hironobu (Tokyo JPX), In-circuit emulator.
  380. Nemecek,Craig; Roe,Steve, In-circuit emulator with gatekeeper based halt control.
  381. Nemecek,Craig; Roe,Steve, In-circuit emulator with gatekeeper for watchdog timer.
  382. Johnson Thomas M. (Tempe AZ) Bakthavathsalu Aravindh (Chandler AZ) Brunner Richard (Gilbert AZ) Garbus Eliot (Scottsdale AZ) Gillespie Byron (Phoenix AZ) Strazdus Stephen J. (Chandler AZ), In-circuit-emulation event management system.
  383. Turner John E. (Beaverton OR) Rutledge David L. (Beaverton OR) Darling Roy D. (Forest Grove OR), In-system programmable logic device.
  384. Wang Chung-Ning ; Platt John C. ; Matic Nada P., Incremental ideographic character input method.
  385. Wang Chung-Ning ; Platt John C. ; Matic Nada P., Incremental ideographic character input method.
  386. Wang Chung-Ning ; Platt John C. ; Matic Nada P., Incremental ideographic character input method.
  387. Lee Ching ; Cedar Yoram, Individually accessible macrocell.
  388. Diamant Erez,ILX ; Prescher Amir,ILX, Information security method and apparatus.
  389. Gradinariu Julian C., Input buffer with stabilized trip points.
  390. Watarai Seiichi,JPX, Input circuit, output circuit, input-output circuit and method of processing input signals.
  391. Huang Joseph ; Cliff Richard G. ; Reddy Srinivas T., Input/output interface circuitry for programmable logic array integrated circuit devices.
  392. Ha Chang W. (Keumjeongku KRX) Moon Joong K. (Songpaku KRX), Input/output macrocell for programmable logic device.
  393. James Beausang ; Harbinder Singh, Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker.
  394. Pesce Michael S. ; Gearhardt Kevin J. ; Kuppinger Jonathan P., Integrated circuit design using a frequency synthesizer that automatically ensures testability.
  395. Kolze Paige A. (San Jose CA), Integrated circuit facilitating simultaneous programming of multiple antifuses.
  396. Kaiser, Robert; Schamberger, Florian, Integrated circuit having a self-test device for carrying out a self-test of the integrated circuit.
  397. Distinti, Robert J; Smith, Harry F, Integrated circuit having circuit blocks that are selectively interconnectable using programming instructions received from a remote location, such as the internet.
  398. Marbot Roland (Versailles FRX), Integrated circuit having controller impedances and application to transceivers, in particular for communication between.
  399. Mou-Shiung Lin TW, Integrated circuit module has common function known good integrated circuit die with multiple selectable functions.
  400. Hull Richard L. (Chandler AZ) Ellison Ryan Scott (Chandler AZ), Integrated circuit pins configurable as a clock input pin and as a digital I/O pin or as a device reset pin and as a dig.
  401. Floyd Jeffery A. (Round Rock TX) Matthews Lloyd P. (Buda TX), Integrated circuit with an active-level configurable and method therefor.
  402. Brannick Dara Joseph,IEX ; Mitchell Patrick Michael,IEX ; Cummins Timothy J.,IEX ; O'Mara Brian John,IEX, Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit.
  403. Kohno, Ryuji; Akai, Kenichiro; Sanada, Yukitoshi; Morelos-Zaragoza, Robert; Michael, Lachlan, Integrated circuit, method of circuit configuration and program thereof.
  404. Whetsel, Lee D., Integrated circuits carrying intellectual property cores and test ports.
  405. Allen Timothy P. (Los Gatos CA) Faggin Federico (Los Altos Hills CA), Integrated device for recognition of moving objects.
  406. Latham, II, Paul W.; Canfield, John C., Integrated device providing current-regulated charge pump driver with capacitor-proportional current.
  407. Perner, Martin, Integrated dynamic memory and operating method.
  408. Bakker Jacobus M. (Eindhoven NLX) Hagedorn Dieter (Hamburg DEX), Integrated microcontroller having a cup-only mode of operation which directly outputs internal timing information for an.
  409. Gorecki, James L.; Yang, Yaohua, Integrated programmable continuous time filter with programmable capacitor arrays.
  410. McLeod,Scott C., Integrated resistance cancellation in temperature measurement systems.
  411. Hibbs,Andrew D.; Matthews,Robert; Jabson,David Matthew, Integrated sensor system for measuring electric and/or magnetic field vector components.
  412. Caldwell,David W., Integrated touch sensor and light apparatus.
  413. Mead Carver A. ; Faggin Federico, Integrating imaging system with phototransistor having wide dynamic range.
  414. Mead Carver A. (Pasadena CA) Faggin Federico (Los Altos Hills CA), Integrating imaging systgem having wide dynamic range with sample/hold circuits.
  415. Mead Carver A. (Pasadena CA) Faggin Federico (Los Altos Hills CA), Integrating photosensor and imaging system having wide dynamic range.
  416. Mead Carver A. (Pasadena CA) Faggin Federico (Los Altos Hills CA), Integrating photosensor and imaging system having wide dynamic range with varactors.
  417. Cheng Yang-Leh ; Cheng Andrew Y., Intelligent real-time graphic-object to database linking-actuator for enabling intuitive on-screen changes and control.
  418. Sullivan Gary, Intelligent window user interface for computers.
  419. Baum, Lawrence S.; Boose, John H.; Boose, Molly L.; Post, Michael D., Intelligent wiring diagram system.
  420. Prakash, Shiv; Burnette, David Gaines; Waters, Simon, Interactive memory allocation in a behavioral synthesis tool.
  421. Young Steven P. ; Bauer Trevor J., Interconnect structure for FPGA with configurable delay locked loop.
  422. Miyazawa, Naoyuki, Interdigital capacitor having a cutting target portion.
  423. Heile Francis B. ; Rawls Tamlyn V., Interface for compiling project variations in electronic design environments.
  424. Voth David W., Interface hardware design using internal and external interfaces.
  425. Molson, Philippe; San, Tony, Interleaver-deinterleaver megacore.
  426. Joshi,Rajiv V.; Ye,Qiuyi; Devgan,Anirudh, Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability.
  427. Miyake, Hideo; Suga, Atsuhiro; Nakamura, Yasuki, Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interrupt.
  428. Redpath Richard J., Intuitive technique for visually creating resource files.
  429. Donohue Thomas E. ; Glad Paul H. ; O'Callaghan James L., Kiosk touch pad.
  430. , LVDS driver for backplane applications.
  431. Ilchmann, Frank; Rösener, Detlef; Ballentin, Ralph, LVDS driver in bipolar and MOS technology.
  432. Reinschmidt,Robert M.; Krishnamurthy,Dilip, LVDS input circuit with extended common mode range.
  433. Hiiragizawa Yasunori,JPX, Large scale integrated circuit having functional blocks controlled with clock signals that conduct setting operations at.
  434. Stansell Galen E. ; Fox J. Kenneth ; Mann Eric N. ; Myers James P. ; Wright Timothy V., Latching inputs and enabling outputs on bidirectional pins with a phase locked loop (PLL) lock detect circuit.
  435. Fujioka Shuzo (Itami JPX), Level converter including wave-shaping circuit and emulator microcomputer incorporating the level converter.
  436. Harald Philipp GB, Level sensing.
  437. Hedberg Mats,SEX, Line receiver circuit with large common mode range for differential input signals.
  438. Platt John C. (Mountain View CA) Wall Michael F. (Sunnyvale CA) Gribble Glenn E. (San Jose CA) Mead Carver A. (Pasadena CA), Linear, continuous-time, two quadrant multiplier.
  439. Williams, Bertrand J.; Dalmia, Kamal; Little, Terry D., Linearized digital phase-locked loop.
  440. Holloway Peter R. ; Subrahmayan Ravi ; Sheehan Gary S., Linearized temperature sensor.
  441. Bisanti, Biagio; Cipriani, Stefano; Coppola, Francesco, Loop filter architecture.
  442. Cordoba Michael V. (Colorado Springs CO) Hardee Kim C. (Colorado Springs CO), Low power Vcc and temperature independent oscillator.
  443. Xin-LeBlanc, Jane, Low power differential-to-single-ended converter with good duty cycle performance.
  444. Ray S. Doug (Austin TX) Peterson Craig M. (Austin TX), Low power, slew rate insensitive power-on reset circuit.
  445. Volk, Andrew M., Low supply voltage differential signal driver.
  446. Francesco Pulvirenti IT, Low supply voltage relaxation oscillator having current mirror transistors supply for capacitors.
  447. Bangs, Joakim; Thompson, John; Filippi, Raymond, Low voltage differential signal (LVDS) input circuit.
  448. Roper, Weston; Feng, Xiaoxin, Low voltage differential signal driver circuit and method.
  449. Dillon, Christopher Daniel, Low voltage differential signaling (LVDS) drivers and systems.
  450. Lo,Hua Jan; Lin,Simon; Chen,June; Chu,Wei Shang, Low voltage differential signaling device with feedback compensation.
  451. Macaluso, Steven Mark, Low voltage differential swing (LVDS) signal driver circuit with low PVT and load sensitivity.
  452. Cook, Richard W.; O'Brien, Stephen J.; Yarbrough, Roy L., Low voltage differential swing (LVDS) signal driver circuit with low PVT sensitivity.
  453. Maher, Kenneth A.; Blake, Anthony, Low voltage receiver circuit and method for shifting the differential input signals of the receiver depending on a common mode voltage of the input signals.
  454. Bryant, Christopher D.; Edenfield, Robin W., Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock.
  455. Dosho,Shiro; Yanagisawa,Naoshi; Toyama,Masaomi; Umehara,Keijiro; Fukui,Masahiro; Yoshikawa,Takefumi; Iwata,Toru; Sakiyama,Shiro; Suzuki,Ryoichi, Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit.
  456. Davis,Bradley Kendall, Low-skew single-ended to differential converter.
  457. Lin Jyhfong,TWX ; Lee Shan-Shan,TWX ; Swei Yuwen,TWX, Low-voltage, low-jitter voltage controlled oscillator.
  458. Anderson Janeen D. W. (Fremont CA) Mead Carver A. (Pasadena CA), MOS device for long-term learning.
  459. Corsi Marco ; Escobar-Bowser Priscilla ; Maclean Kenneth G., MOSFET single-pair differential amplifier having an adaptive biasing scheme for rail-to-rail input capability.
  460. Kiani Khusrow (Oakland CA) Balicki Janusz K. (San Jose CA) Nouban Behzad (Fremont CA) Li Ken (Santa Clara CA), Macrocell comprised of two look-up tables and two flip-flops.
  461. Kapusta Richard L. ; Jones Christopher W., Macrocell having a dual purpose input register for use in a logic device.
  462. Ely,David; McCaughan,Gareth, Magnetic calibration array.
  463. Hase Kenichi (Yokohama JPX) Miyazawa Syoichi (Yokohama JPX) Horita Ryutaro (Yokohama JPX) Kojima Shinichi (Takasaki JPX) Hirano Akihiko (Fujisawa JPX) Uragami Akira (Takasaki JPX), Magnetic disk storage apparatus with phase sync circuit having controllable response characteristics.
  464. Kanda Masahiko (Osaka JPX), Meat freshness measuring apparatus.
  465. James M. Cleeves, Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays.
  466. Krishnan, Rengarajan S., Memory based phase locked loop.
  467. Rangasayee Krishna ; Bielby Robert N., Memory cells configurable as CAM or RAM in programmable logic devices.
  468. Sample, Stephen P.; Bershteyn, Mikhail; Butts, Michael R.; Bauer, Jerry R., Memory circuit for use in hardware emulation system.
  469. Martin Alan (Plymouth GBX) Albon Richard (Tavistock GBX), Memory defect detection arrangement.
  470. Lin, Sharon Sheau-Pyng; Tseng, Ping-Sheng, Memory mapping system and method.
  471. Black Darryl P. (Merrimack NH) Ricci Elizabeth G. (Bedford MA), Method an apparatus for specification of communication parameters.
  472. Dancea,Ioan, Method and VLSI circuits allowing to change dynamically the logical behavior.
  473. Rajsuman, Rochit; Yamoto, Hiroaki, Method and apparatus for SoC design validation.
  474. Ludolph Frank, Method and apparatus for accessing information and items across workspaces.
  475. Maddocks,Peter M.; Ferguson,David P.; Maddocks,Steve; Weitzel,William G., Method and apparatus for analyzing machine control sequences.
  476. Mitsuta Toru (Hitachi JPX) Wada Yutaka (Hitachi JPX) Kobayashi Yasuhiro (Katsuta JPX), Method and apparatus for assisting layout design.
  477. Bold Stephen L.,GBX ; Dane Mark W. P.,GBX ; Reynolds Michael J.,GBX ; Paraskeva Mark,GBX ; Stewart James,GBX, Method and apparatus for automatically cross-referencing graphical objects and HDL statements.
  478. Evans Keith M. ; Grundy Kevin P., Method and apparatus for bridging a plurality of buses and handling of an exception event to provide bus isolation.
  479. Kusbel,Patrick J., Method and apparatus for calibrating a reference oscillator.
  480. Malang, Keith; Hutsell, Larry, Method and apparatus for calibrating piezoelectric driver in dual actuator disk drive.
  481. Wilson,Brent; Highley,Paul; Fernald,Kenneth W., Method and apparatus for calibration of a low frequency oscillator in a processor based system.
  482. Signore Bruce D. (Austin TX) Swanson Eric J. (Austin TX), Method and apparatus for calibration of a monolithic voltage reference.
  483. Snider,Gregory S., Method and apparatus for compiling source code to configure hardware.
  484. Lynch John ; Franke David, Method and apparatus for configuring systems.
  485. Dabral Sanjay ; Sampath Dilip K. ; Cheng Christopher, Method and apparatus for configuring the pinout of an integrated circuit.
  486. Foote, Geoffrey; Gillespie, David W., Method and apparatus for controlling a display of data on a display screen.
  487. Fetterman H. Scott ; Rich David A., Method and apparatus for controlling the common-mode output voltage of a differential buffer.
  488. Gerpheide George E. ; Johnson Rick L. ; McDonald Marty, Method and apparatus for data input.
  489. Keller, Eric R.; Patterson, Cameron D., Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices.
  490. Manghirmalani Ravi ; Garg Atul R. ; Dere Judy Y. ; Do Minh A. ; Leong Leon Y. K., Method and apparatus for determining the health of a network.
  491. Williams, Anthony D., Method and apparatus for developing and placing a circuit design.
  492. Guddat Douglas A. ; Cleary James M. ; Israeli Tsafrir,ILX, Method and apparatus for direct access test of embedded memory.
  493. Lambert, Mark; Hanau, Paul, Method and apparatus for displaying and manipulating multiple geometric constraints of a mechanical design.
  494. Cameron Charles J. ; Catlin Gary M., Method and apparatus for emulating a frequency modulation device.
  495. Bross, Kevin W.; Johnson, Monte G., Method and apparatus for emulating a local data port.
  496. Barnett Philip,GBX ; Green Andy,GBX, Method and apparatus for evaluating software programs for semiconductor circuits.
  497. Smith Paul ; Romascan Edward, Method and apparatus for extending the signal path of a peripheral component interconnect bus to a remote location.
  498. Torres Robert J. (Colleyville TX), Method and apparatus for facilitating operator reconfiguration of a graphical user interface in a data processing system.
  499. Low, Eng Chuan; Cheah, Jonathon; Yang, Shih-Tsung; Fatt, Christopher Yong Soon, Method and apparatus for filter tuning.
  500. Ogami,Kenneth Y.; Anderson,Doug; Pleis,Matthew; Hood, III,Frederick Redding, Method and apparatus for generating microcontroller configuration information.
  501. Davidson, Scott A.; Mickelson, Steven C.; Sarkinen, Gregg T.; Sarkinen, Scott A.; Sigel, Robert W., Method and apparatus for graphically programming a programmable circuit.
  502. Chapdelaine Eugene R. ; O'Connor Christopher J. ; Burger Robert J. ; Hawley Stephen A., Method and apparatus for improving the performance of an aperture monitoring system.
  503. Westerman Wayne ; Elias John G., Method and apparatus for integrating manual input.
  504. Rostoker Michael D. (Boulder Creek CA) Gluss David (Woodside CA) Harrington Tom (Mountain View CA), Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC.
  505. Mar, Monte, Method and apparatus for local and global power management in a programmable analog circuit.
  506. Allen Timothy P. (Palo Alto CA) Wall Michael F. (Sunnyvale CA) Faggin Federico (Los Altos Hill CA), Method and apparatus for performing neighborhood operations on a processing plane.
  507. Stone Maureen C. (Los Altos CA) Bier Eric A. (Mountain View CA) Fishkin Kenneth P. (Redwood City CA) DeRose Anthony (Seattle WA), Method and apparatus for producing a composite second image in the spatial context of a first image.
  508. Snyder,Warren, Method and apparatus for programming a flash memory.
  509. John B. Berry ; James R. Booth ; Keith B. Hardin ; John P. Richey, Method and apparatus for providing a clock generation circuit for digitally controlled frequency or spread spectrum clocking.
  510. Marvin Dennis F. (Carol Stream IL) Russell Daniel J. (Lake Zurich IL), Method and apparatus for providing a modified temperature compensation signal in a TCXO circuit.
  511. Rangan,P. Venkat; Sharma,Manoj; Rajan,Sreeranga P.; Wu,Jonathan, Method and apparatus for providing calculated and solution-oriented personalized summary-reports to a user through a single user-interface.
  512. Kapusta Richard L. ; Jones Christopher W., Method and apparatus for providing clock signals to macrocells of logic devices.
  513. Chew, Chee H.; Bastiaanse, Elizabeth A.; Blum, Jeffrey R.; Keyser, Greg A.; Lui, Charlton E.; Parker, Kathryn L.; Sharpe, Timothy D.; Zuberec, Sarah E., Method and apparatus for providing context menus on a pen-based device.
  514. Yaacov (Jacob) Greidinger ; Ara Markosian ; Jon Frankle, Method and apparatus for providing multiple electronic design solutions.
  515. Christensen Reed K. ; Wolper Andre Eberhard, Method and apparatus for providing precise fault tracing in a superscalar microprocessor.
  516. Huboi, Peter A.; Sharma, Shailendra; Chan, Laurence C.; Epplett, John, Method and apparatus for providing user specific web-based help in a distributed system environment.
  517. Lim, Chee How; Wong, Keng L.; Parker, Rachael, Method and apparatus for reducing lock time in dual charge-pump phase-locked loops.
  518. Olson Dana J. ; Seguine Dennis R., Method and apparatus for removing baseline wander from an egg signal.
  519. Allen Timothy ; Day Shawn P. ; Ferrucci Aaron T., Method and apparatus for scroll bar control.
  520. Merryman, Kenneth E.; Lautzenheiser, Ted G.; Engh, Michael K., Method and apparatus for selectively providing hierarchy to a circuit design.
  521. Hrustich John (Endicott NY) Jackson ; Jr. Earl W. (Apalachin NY), Method and apparatus for synchronizing clocks prior to the execution of a flush operation.
  522. Craig L. Chaiken, Method and apparatus for testing ASL plug and play code in an ACPI operating system.
  523. Fleisher Evgeny G., Method and apparatus for testing a logic design of a programmable logic device.
  524. Profit ; Jr. Jack H., Method and apparatus for testing software.
  525. Hanna, Stephen Dale, Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits.
  526. Comino Vittorio ; Shulman Dima David ; Walker Susan Jeanne, Method and apparatus for tuning a continuous time filter.
  527. Patel Chandresh (3480 Granada Ave. ; #249 Santa Clara CA 95051), Method and apparatus to emulate VLSI circuits within a logic simulator.
  528. Barbier Jean,FRX ; Lepape Olivier,FRX ; Reblewski Frederic,FRX, Method and apparatus tracing any node of an emulation.
  529. Robert Payne ; Mark Bapst ; Timothy Pontius, Method and arrangement for rapid silicon prototyping.
  530. Sullam, Bert, Method and circuit for allowing a microprocessor to change its operating frequency on-the-fly.
  531. Jackson Daniel K. (Hillsboro OR), Method and circuit for checking integrated circuit chips.
  532. Eberlein, Matthias, Method and circuit for compensating MOSFET capacitance variations in integrated circuits.
  533. Erd챕lyi,J찼nos; Horv찼th,Andr찼s Vince, Method and circuit for generating a higher order compensated bandgap voltage.
  534. Kuo,Shu Hua; Li,Jui Ting, Method and circuit for measuring capacitance and capacitance mismatch.
  535. Moyal,Nathan; Stiff,Jonathon C., Method and circuit for rapid alignment of signals.
  536. Moyal, Nathan, Method and circuit for reducing the power up time of a phase lock loop.
  537. Sullam, Bert; Kutz, Harold; Mar, Monte, Method and circuit for synchronizing a write operation between an on-chip microprocessor and an on-chip programmable analog device operating at different frequencies.
  538. Sanchez,Stephen J.; Hiser,Daryl, Method and circuit for trimming a current source in a package.
  539. Chen,Yi Chang; Yuan,Kuo Yuan; Liao,Ying Chien; Lai,Shih Jung, Method and device for clock calibration.
  540. Warren Robert,GBX, Method and device for communicating across a chip boundary including a serial-parallel data packet converter having flow control logic.
  541. Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, Method and structure for configuring FPGAS.
  542. Zizzo, Claudio, Method and system for chip design using remotely located resources.
  543. Dangelo Carlos ; Watkins Daniel ; Mintz Doron, Method and system for creating and validating low level description of electronic design from higher level, behavior-or.
  544. Rostoker Michael D. ; Dangelo Carlos ; Bair Owen S., Method and system for creating and verifying structural logic model of electronic design from behavioral description, i.
  545. Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Watkins Daniel R. (Los Altos CA), Method and system for creating, deriving and validating structural description of electronic system from higher level, b.
  546. Bergeron Louise M. ; Klein Mark P. ; Orsillo Paul H., Method and system for database access.
  547. Roe,Steve; Pleis,Matt; Nemecek,Craig, Method and system for debugging through supervisory operating codes and self modifying codes.
  548. Cohen Leonard George ; Schwartz Morton I. ; Wang Yan ; Yaffe Henry Howard, Method and system for designing and analyzing optical application specific integrated circuits.
  549. Barrass,Hugh; Schwartz,David A., Method and system for distributing data communications utilizing a crossbar switch.
  550. Gorczyca Robert ; Rashid Aamir Arshad ; Rodgers Kevin Forress ; Warnsman Stuart ; Weaver Thomas Van, Method and system for dynamically reconfiguring a cluster of computer systems.
  551. Bakker Jacobus M.,NLX, Method and system for emulating microcontrollers.
  552. Robertson, William H.; Plymale, James M., Method and system for facilitating electronic circuit and chip design using remotely located resources.
  553. John W Bockhaus ; Jay Fleischman, Method and system for flexible control of BIST registers based upon on-chip events.
  554. Jacomb Hood,Anthony W., Method and system for flexibly distributing power in a phased array antenna system.
  555. Dellinger Eric F. ; Iwanczuk Roman, Method and system for generating a programming bitstream including identification bits.
  556. Brennan Thomas C. (Rochester MN), Method and system for indicating a status of a circuit design.
  557. Hwang, L. James; Sanchez, Reno L., Method and system for integrating cores in FPGA-based system-on-chip (SoC).
  558. Kutz, Harold; Snyder, Warren, Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller.
  559. Jeffrey Thomas Galea ; Noah Christopher Woodman ; James Richard Reid ; James Malcolm Sprinkle, Method and system for modeling data.
  560. Snyder, Warren; Rouse, Mark, Method and system for programming a memory device.
  561. Hwang,L. James; Sanchez,Reno L., Method and system for resource allocation in FPGA-based system-on-chip (SoC).
  562. Gristede George D. ; Hwang Wei ; Tretz Christophe Robert, Method and system for selecting sizes of components for integrated circuits.
  563. Sun Cheng-Hung TW; Fang Chien-Kuo TW; Tai Chia-Yang TW, Method and system for translating the format of the content of document file.
  564. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Douglas H., Method and system for using a graphics user interface for programming an electronic device.
  565. Bjorksten Andrew A. ; Zoric Brian A. ; Schmookler Martin S., Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit t.
  566. Bauchot, Frederic; Harari, Albert, Method and system in an electronic spreadsheet for processing different cell protection modes.
  567. Schubert, Nils Endric; Beardslee, John Mark; Koch, Gernot Heinrich; Poeppe, Olaf, Method and user interface for debugging an electronic system.
  568. Snyder, Warren, Method for applying instructions to microprocessor in test mode.
  569. Schneider, Stanley A.; Chen, Vincent W.; Pardo-Castellote, Gerardo; Wang, Howard H.; Joshi, Rajive, Method for building a real-time control system with mode and logical rate.
  570. Allen Timothy P. ; Cser James B., Method for changing the weight of a synaptic element.
  571. Zimmermann Jurgen,DEX ; Grote Walter,DEX, Method for completely reprogramming an erasable, non-volatile memory.
  572. Lawman Gary R. ; Linoff Joseph D. ; Wells Robert W., Method for configuring circuits over a data communications link.
  573. Bartz,Manfred; Zhaksilikov,Marat; Roe,Steve; Ogami,Kenneth Y.; Pleis,Matthew A.; Anderson,Douglas H., Method for designing a circuit for programmable microcontrollers.
  574. Kutz, Harold; Snyder, Warren, Method for efficient supply of power to a microcontroller.
  575. Kutz,Harold; Snyder,Warren, Method for efficient supply of power to a microcontroller.
  576. Snyder,Warren, Method for entering circuit test mode.
  577. Skrovan Joseph C. ; Parker Allan, Method for event-related functional testing of a microprocessor.
  578. Bartz, Manfred; Zhaksilikov, Marat; Roe, Steve; Ogami, Kenneth Y.; Pleis, Matthew A.; Anderson, Douglas H., Method for facilitating microcontroller programming.
  579. Allison,Michael S; Silva,Stephen; Hack,Stephen Patrick, Method for generating a read only memory image.
  580. Knapp Steven K. (Santa Clara CA) Seidel Jorge P. (San Jose CA) Kelem Steven H. (Los Altos Hills CA), Method for generating logic modules from a high level block diagram.
  581. Ezell Richard William, Method for initializing an electronic device using a dual-state power-on-reset circuit.
  582. Merkin,Aaron E., Method for maximizing server utilization in a resource constrained environment.
  583. Winklhofer Ernst,ATX ; Philipp Harald Arnulf,ATX ; Tschetsch Horst,ATX, Method for optically detecting gas bubbles moving in a coolant.
  584. Moyal, Nathan Y.; Gehring, Mark R.; Moen, Russell; Ragan, Lawrence, Method for phase locking in a phase lock loop.
  585. Thurnhofer Stefan ; Whalen Shaun P., Method for powering-up a microprocessor under debugger control.
  586. Moyal Nathan Y. ; Williams Bertrand J., Method for reducing static phase offset in a PLL.
  587. Woodward James S., Method for reprogramming flash ROM in a personal computer implementing an EISA bus system.
  588. Takagi, Shusaku; Tsuzaki, Kaneaki; Inoue, Tadanobu, Method for setting shape and working stress, and working environment of steel member.
  589. Hong Sung-In,KRX ; Choi Young-Jun,KRX, Method for simultaneously programming plural flash memories having invalid blocks.
  590. Sullam, Bert, Method for synchronizing and resetting clock signals supplied to multiple programmable analog blocks.
  591. Bauwens, Peter; Chichkov, Anton, Method for testing integrated circuits with an automatic test equipment.
  592. Negut,Alina I.; Georgescu,Sorin S.; Eftimie,Sabin A., Method for trimming the temperature coefficient of a floating gate voltage reference.
  593. Andersson, Karl A. I.; Roos, Sture G., Method of and an arrangement in a telecommunication system for regulating the phase position of a controlled signal in relation to a reference signal.
  594. Tabata Kuniaki (Tokyo JPX) Machida Tetsuo (Sagamihara JPX) Takeda Haruo (Machida JPX) Takada Naoki (Hadano JPX) Okada Yasuyuki (Sagamihara JPX), Method of and apparatus for enlarging/reducing two-dimensional images.
  595. Tamura, Hiroaki, Method of and apparatus for testing CPU built-in RAM mixed LSI.
  596. Patrick H. Buffet ; Paul E. Dunn ; Joseph Natonio ; Robert A. Proctor ; Gulsun Yasar, Method of assigning integrated circuit I/O signals in an integrated circuit package.
  597. Kageshima Atsushi,JPX, Method of estimating power consumption of each instruction processed by a microprocessor.
  598. Scalzi Casper Anthony ; Plambeck Kenneth Ernest, Method of executing perform locked operation instructions for supporting recovery of data consistency if lost due to pro.
  599. Razmik Ahanessians ; Marcel A. LeBlanc, Method of generating customized megafunctions.
  600. Wei-Wei Zhuang ; Fengyan Zhang ; Sheng Teng Hsu ; Tingkai Li, Method of metal oxide thin film cleaning.
  601. Sonoda Kenichiro,JPX, Method of simulating an integrated circuit for error correction in a configuration model, and a computer-readable recording medium.
  602. Gross Kimberly L. (Raleigh NC) Sullivan Kirk D. (Orlando FL), Method of testing programs in a distributed environment.
  603. Richard S. Graham ; Rick Lee Pray, Method to collate and extract desired contents from heterogeneous text-data streams.
  604. Alimpich Claudia C. ; Boldt Gerald D. ; Doescher Calvin Larry ; Goddard Joan Stagaman ; Vigil Luana L. ; Vo Minh Trong ; Wittig James Philip, Method, apparatus and application for object selective but global attribute modification.
  605. Scott, Paul H.; Raza, S. Babar, Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector.
  606. Marneweck Willem J. ; Smit Willem ; Chen Meiling, Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an eeprom.
  607. Taylor,Julian S., Method, system, and program for generating a user interface.
  608. Carney, Dennis Michael; Nguyen, Ryan Hoa, Method, system, program, and data structures for reconfiguring output devices in a network system.
  609. Meyers, Steven; Moyal, Nathan Y., Method/architecture for a low gain PLL with wide frequency range.
  610. Dole, Harry, Methodology server based integrated circuit design.
  611. Ludolph Frank E. ; Tharakan George, Methods and apparatus for a window access panel.
  612. Stellenberg Daniel S. ; Karchmer David, Methods and apparatus for automatically generating interconnect patterns in programmable logic devices.
  613. Gerpheide George E., Methods and apparatus for data input.
  614. Gerpheide George E. (3481 S. Monte Verde Dr. Salt Lake City UT 84109), Methods and apparatus for data input.
  615. Fiorella, III, Daniel Charles; Gebhardt, Jr., Ronald L.; McGregor, Jr., Marlin F., Methods and apparatus for upgrading firmware in an embedded system.
  616. Kenneth S. McElvain ; Robert Erickson, Methods and apparatuses for designing integrated circuits.
  617. Reinaldo A. Bergamashi/Rab ; Subhrajit Bhattacharya ; Jean-Marc R. Daveau FR; William R. Lee, Methods and arrangements for automatic synthesis of systems-on-chip.
  618. Itoh Sakae,JPX ; Kanzaki Teruaki,JPX ; Akatsuki Tadayuki,JPX ; Sakai Tatsuya,JPX ; Numata Tsutomu,JPX ; Nakamura Yasuhiro,JPX, Microcomputer.
  619. Kuwahara Kazuyoshi (Kanagawa JPX), Microcomputer free from control of central processing unit (CPU) for receiving and writing instructions into memory inde.
  620. Meli, Louis Marcel, Microcomputer with test instruction memory.
  621. Warren S. Snyder ; Frederick D. Jaccard, Microcontroller development system and applications thereof for development of a universal serial bus microcontroller.
  622. Chien Yung-Ping S. ; Connor William D. S. ; Jeffares Christopher D., Microcontroller development tool using software programs.
  623. Elmer Thomas I. (Santa Clara CA) Nguyen Tuan T. (Milpitas CA) Lin Rung-Pan (San Jose CA), Microcontroller device having remotely programmable EPROM and method for programming.
  624. Dey Shankar (San Jose CA), Microcontroller emulator for plural device architecture configured by mode control data and operated under control code.
  625. Gauthier Lloyd W. ; Wakeland Carl K. ; Hayat Faheem ; Tobias David F., Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface.
  626. Kutz,Harold; Mar,Monte, Microcontroller having an on-chip high gain amplifier.
  627. Klapproth Peter (Eindhoven NLX) Zandveld Frederik (Eindhoven NLX) Bakker Jacobus M. (Eindhoven NLX) Van Loo Gerardus C. (Eindhoven NLX), Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions.
  628. Birns Neil E. ; Mizrahi-Shalom Ori K., Microcontroller system for performing operations of multiple microcontrollers.
  629. Eugene Feng ; Gary Phillips, Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space.
  630. Tsai Hsi-Jung,TWX, Microcontroller with programmable embedded flash memory.
  631. Grimmer ; Jr. George G. ; Rhoades Michael W., Microcontroller with security logic circuit which prevents reading of internal memory by external program.
  632. Miyamori Takashi,JPX ; Yano Tatsuo,JPX, Microprocessor and debug system.
  633. Jose Maria Insenser Farre ES; Julio Faura Enriquez ES, Microprocessor based mixed signal field programmable integrated device and prototyping methodology.
  634. Graham Kirsch GB; Simon Martin Kershaw, Microprocessor debugging mechanism employing scan interface.
  635. Kershaw, Simon Martin; Kirsch, Graham; Slade, Brendon, Microprocessor development systems.
  636. Andrew Michael Jones GB; David Alan Edwards GB; Michael David May GB, Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port.
  637. Thompson Robert R. (Largo FL), Microprocessor having self-programmed eprom.
  638. Dreyer Robert S. (Sunnyvale CA) Alpert Donald B. (Santa Clara CA) Modi Nimish H. (San Jose CA) Tripp Mike J. (Forest Grove OR), Microprocessor with an external command mode for diagnosis and debugging.
  639. El-Ayat Khaled A. (Cupertino CA), Mixed mode analog/digital programmable interconnect architecture.
  640. Naglestad Mark B. (Mission Viejo CA) Bohac ; Jr. Frank J. (Laguna Hills CA) Aralis James M. (Mission Viejo CA) Moriwaki Bert S. (Laguna Niguel CA) Calabretta Frank J. (Costa Mesa CA) Troutman Bruce L, Mixed signal integrated circuit architecture and test methodology.
  641. Mason, Jeffrey M.; Lass, Steve E.; Talley, Bruce E.; Bennett, David W., Modular design method and system for programmable logic devices.
  642. Muradali Fidel ; Aitken Robert C., Modular embedded test system for use in integrated circuits.
  643. van der Wal Gooitzen Siemen ; Hansen Michael Wade ; Piacentino Michael Raymond ; Brehm Frederic William, Modular parallel-pipelined vision system for real-time video processing.
  644. Caldwell, David W.; Bird, Kevin C.; Schaefer, William D., Molded/integrated touch switch/control panel assembly and method for making same.
  645. Ruby,Paul; Eilert,Sean, Monitoring the threshold voltage of frequently read cells.
  646. Pearce Lawrence G. ; Hemmenway Donald F., Monolithic class D amplifier.
  647. Nguyen Cong Dinh ; Brightman Stephen Christopher, Monolithic oscillator utilizing frequency-locked loop feedback network.
  648. England James M. C.,GBX ; Dames Andrew N.,GBX ; Ely David T. E.,GBX ; Burwell Malcolm,GBX ; Foote Geoffrey,GBX, Motor control system.
  649. Seigneret,Franck; Khalifa,Nabil; Ayinala,Sivayya; Kolli,Praveen, Multi-channel DMA with shared FIFO.
  650. Jerry L. Mizell ; David Lauson ; Kent Fisher ; Larry D. Lewis, Multi-function coding element and an associated telecommunications network.
  651. Schade ; Jr. Otto H. (N. Caldwell NJ), Multi-mode relaxation oscillator.
  652. Sugasawa Yasuo,JPX, Multi-phase clock generator circuit.
  653. Gibson Garnet Frederick Randall,CAX, Multi-port random access memory with shadow write test mode.
  654. Agrawal Om P. ; Sharpe-Geisler Bradley A., Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices.
  655. Westerman, Wayne Carl; Elias, John Greer, Multi-touch system and method for emulating modifier keys via fingertip chords.
  656. Hiroo Mochida JP, Multichip semiconductor device.
  657. Hildebrant, Paul; Li, Jian; Klein, Hans W., Multimode output stage converting differential to single-ended signals using current-mode input signals.
  658. Yamagiwa Akira (Hadano JPX) Okabe Toshihiro (Hadano JPX), Multiphase clock distribution for VLSI chip.
  659. Lavelle Gary E. ; Conklin Peter S. ; Hass Brian D. ; Walsh ; III John E., Multiple access electronic lock system.
  660. Lada ; Jr. Henry F. (Houston TX) Le Hung Q. (Houston TX) Garrett James H. (Spring TX) Gromala John M. (Houston TX), Multiple frequency phase-locked loop clock generator with stable transitions between frequencies.
  661. Miller,William V., Multiple master buses and slave buses transmitting simultaneously.
  662. Nebrigic, Dragan Danilo; Jevtitch, Milan Marcel; Gartstein, Vladimir; Milam, William Thomas; Sherrill, James Vig; Busko, Nicholas; Hansen, Peter, Multiple output dynamically regulated charge pump power converter.
  663. Bowers Richard, Multiple use chip socket for integrated circuits and the like.
  664. Kutz, Harold; Mar, Monte; Snyder, Warren, Multiple use of microcontroller pad.
  665. Gephardt Douglas D. ; Schmidt Rodney W., Multiprocessing system employing an adaptive interrupt mapping mechanism and method.
  666. Suk Hyun Hong, Multipurpose processor for motion estimation, pixel processing, and general processing.
  667. Terence Chan, Multithreaded, mixed hardware description languages logic simulation on engineering workstations.
  668. Harada Hiroyuki (Kanagawa JPX), N-phase modulated signal demodulation system with carrier reproduction.
  669. Wilson Daniel B., Navigation between property pages with tabs and menus.
  670. Rajarajan, Vij; Nedungadi, Kishnan; Kiernan, Casey; MacMahon, Mel; Johnston, James; Gallagher, Lauren; Hodge, Kevin; Martino, Tom; Hall, Annette B.; Rohwer, Cary; Zimnickas, Audrius, Navigation tool for accessing workspaces and modules in a graphical user interface.
  671. Hino, Takehisa; Koizumi, Yutaka; Kobayashi, Toshiharu; Nakazawa, Shizuo; Harada, Hiroshi; Ishiwata, Yutaka; Yoshioka, Yomei, Nickel-base single-crystal superalloys, method of manufacturing same and gas turbine high temperature parts made thereof.
  672. Allison Nigel J. (Austin TX) Gray Rand L. (Austin TX) Hartvigsen Jay A. (Austin TX), No-chip debug peripheral which uses externally provided instructions to control a core processing unit.
  673. Szeto Kinyue ; Gracey ; III Charles M. ; Cheng Chuck C. W., Non-intrusive in-system debugging for a microcontroller with in-system programming capabilities using in-system debugging circuitry and program embedded in-system debugging commands.
  674. Hunsaker Scott W. (Boulder CO) Kulik ; III Stephan (Louisville CO) Martin Alan D. (Lafayette CO) Totel Craig A. (Westminster CO), Non-invasive software update apparatus.
  675. Chevallier, Christophe J., Non-volatile memory with test rows for disturb detection.
  676. Watanabe Kazuo,JPX, Non-volatile semiconductor memory device.
  677. Snyder, Warren, Noninterfering multiply-MAC (multiply accumulate) circuit.
  678. Gupta,Arun K.; Uppal,Rajiw K.; Parikh,Devang I., Object oriented based, business class methodology for generating quasi-static web pages at periodic intervals.
  679. Miller Robert J. (Fremont CA) Bisset Stephen (Palo Alto CA) Allen Timothy P. (Los Gatos CA) Steinbach Gnter (Palo Alto CA), Object position and proximity detector.
  680. Allen Timothy P. ; Gillespie David ; Miller Robert J. ; Steinbach Gunter, Object position detection system and method.
  681. Allen Timothy P. ; Gillespie David ; Miller Robert J. ; Steinbach Gunter, Object position detector.
  682. Miller Robert J. (Fremont CA) Bisset Stephen (Palo Alto CA) Allen Timothy P. (Los Gatos CA) Steinbach Gnter (Palo Alto CA), Object position detector.
  683. Miller Robert J. (San Jose CA) Bisset Stephen J. (Los Altos CA), Object position detector.
  684. Miller Robert J. ; Bisset Stephen J., Object position detector.
  685. Schediwy Richard R. ; Pritchard Jeffrey O. ; Kao Ting ; Allen Timothy P. ; Platt John C., Object position detector.
  686. Gillespie David (Palo Alto CA) Allen Timothy P. (Los Gatos CA) Miller Robert J. (Fremont CA) Faggin Federico (Los Altos CA), Object position detector with edge motion feature.
  687. David W. Gillespie ; Timothy P. Allen ; Ralph C. Wolf ; Shawn P. Day, Object position detector with edge motion feature and gesture recognition.
  688. David W. Gillespie ; Timothy P. Allen ; Ralph C. Wolf ; Shawn P. Day, Object position detector with edge motion feature and gesture recognition.
  689. Gillespie David (Palo Alto CA) Allen Timothy P. (Los Gatos CA) Wolf Ralph (Palo Alto CA), Object position detector with edge motion feature and gesture recognition.
  690. Gillespie David W. ; Allen Timothy P. ; Wolf Ralph C. ; Day Shawn P., Object position detector with edge motion feature and gesture recognition.
  691. Gillespie David W. ; Allen Timothy P. ; Wolf Ralph C. ; Day Shawn P., Object position detector with edge motion feature and gesture recognition.
  692. Gillespie, David W.; Allen, Timothy P.; Wolf, Ralph C.; Day, Shawn P., Object position detector with edge motion feature and gesture recognition.
  693. Gillespie, David W.; Allen, Timothy P.; Wolf, Ralph C.; Day, Shawn P., Object position detector with edge motion feature and gesture recognition.
  694. Gillespie,David W.; Allen,Timothy P.; Wolf,Ralph C.; Day,Shawn P., Object position detector with edge motion feature and gesture recognition.
  695. Harenberg Donald D. (Placentia CA) Watson George A. (Fullerton CA) Bindloss Keith M. (Irvine CA) Folwell Dale E. (Placentia CA), On-chip debug port.
  696. Wenzel, Andreas; Chesters, Eric; Fleck, Rod G.; Sheedy, Gary, On-chip debug system.
  697. Dreps Daniel M. (Endicott NY) Rizzo Raymond P. (Vestal NY), On-chip voltage controlled oscillator.
  698. Allen Timothy P. (Los Gatos CA) Cser James B. (Santa Clara CA), One-transistor adaptable analog storage element and array.
  699. Allen Timothy P. ; Cser James B., One-transistor adaptable analog storage element and array.
  700. Stiff,Jonathon, Open loop bandwidth test architecture and method for phase locked loop (PLL).
  701. Philipp Harald (Aloha OR), Optical fiber test instrument calibrator.
  702. Philipp Harald (15320 NE. 11th ; Apt. K326 Bellevue WA 98007), Optical motion sensor.
  703. Dougherty Dawn K. (South Burlington VT), Optimized automated macro embedding for standard cell blocks.
  704. Varadarajan Ravi ; Thompson Robert, Optimized placement and routing of datapaths.
  705. Newberg, Irwin L.; Mellema, Dwight J., Opto-electronic distributed crossbar switch.
  706. Winklhofer Ernst,ATX ; Philipp Harald Arnulf,ATX ; Kreitel Michael,DEX, Optoelectric measuring device for monitoring combustion processes.
  707. Philipp, Harald; Winklhofer, Ernst; Baumgartner, Martin, Optoelectronic measuring device.
  708. Plimon Anton (Graz ATX) Philipp Harald A. (Wegersfeld ATX) Winklhofer Ernst (St. Johann ob Hohenburg/Stmk. ATX), Optoelectronic measuring device for monitoring a combustion chamber.
  709. Goldman Richard,GBX ; Wilson Robin,GBX, Oscillator circuit having trimmable capacitor array receiving a reference current.
  710. Namura Yasuaki,JPX ; Fukuda Hideyuki,JPX, Oscillator circuit with first and second frequency control elements.
  711. Hauck, Lane T., Oscillator tuning method.
  712. Nolan James B. ; Ellison Ryan Scott ; Pyska Michael S., Oscillator with clock output inhibition control.
  713. Tomita Takashi,JPX, Output circuit for a transmission system.
  714. Owen, William H., Output voltage compensating circuit and method for a floating gate reference voltage generator.
  715. Sander, Wendell B., PLL bandwidth switching.
  716. Wilson, James E.; Cowe, Tomasz, PLL lockout watchdog.
  717. Arcus,Christopher G., PLL with built-in filter-capacitor leakage-tester with current pump and comparator.
  718. Kan,Kwok Kei Toby; Leung,Tak Ming, PWM regulator with discontinuous mode and method therefor.
  719. Spinney Barry A. (Wayland MA) Simcoe Robert J. (Westboro MA) Thomas Robert E. (Hudson MA) Varghese George (Bradford MA), Packet format in hub for packet data communications system.
  720. Mead Carver A. (Pasadena CA) Wolf Ralph (Palo Alto CA) Allen Timothy P. (Los Gatos CA), Paintbrush stylus for capacitive touch sensor pad.
  721. Mann Daniel, Parallel and serial debug port on a processor.
  722. Hori Toshikazu ; Paillet Guy ; Woo Jeffrey M., Parallel associative learning memory for a standalone hardwired recognition system.
  723. Nakagoshi Junji (Tokyo JPX) Hamanaka Naoki (Tokyo JPX) Chiba Hiroyuki (Koyasu JPX) Higuchi Tatsuo (Fuchu JPX) Shutoh Shinichi (Kokubunji JPX) Ogata Yasuhiro (Akishima JPX) Takeuchi Shigeo (Hannou JPX, Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks an.
  724. Callaway ; Jr. Edgar H. (11524 Clear Creek Pl. Boca Raton FL 33428) Pace Gary L. (17640 Lake Park Rd. Boca Raton FL 33487) Hughes James D. (5349 Cedar Lake Rd. #12-26 Boynton Beach FL 33437), Peak and valley signal measuring circuit using single digital-to-analog converter.
  725. John C. Platt, Pen drawing computer input device.
  726. Yee, Oceager P.; Ma, Zhigang, Peripheral breakpoint signaler.
  727. Duffy Michael L. ; Navabi Mohammad J., Phase locked loop (PLL) with linear parallel sampling phase detector.
  728. Duffy, Michael L.; Navabi, Mohammad J., Phase locked loop (PLL) with linear parallel sampling phase detector.
  729. Joseph Chan GB; Richard Francis Bastable GB, Phase locked loop clock extraction.
  730. O'Sullivan Eugene,JPX, Phase locked loop using a schmitt trigger block.
  731. Tachimori, Hiroshi, Phase-locked loop circuit and delay-locked loop circuit.
  732. Knapp David J. ; Susanto Tony ; Trager David S., Phase-locked loop with protected output during instances when the phase-locked loop is unlocked.
  733. Gotz, Edmund; Memmler, Bernd; Schonleber, Gunter, Phase-locked loop with short transient recovery duration and small interference signal component.
  734. Nihei,Yasuhiro; Ishida,Masaaki, Pixel clock generation device causing state transition of pixel clock according to detected state transition and phase data indicating phase shift amount.
  735. O\Callaghan James L. (Salt Lake City UT), Portable computer touch pad attachment.
  736. Shibuya Toshiyuki,JPX, Portable electronic apparatus and charge controlling method for portable electronic apparatus.
  737. David T. E. Ely GB; Ross P. Jones GB; James M. C. England GB; Alexander W. McKinnon GB; Robert M. Pettigrew GB; Andrew N. Dames GB; Andrew R. L. Howe GB, Position detector.
  738. Ely,David T. E.; Jones,Ross P.; England,James M. C.; McKinnon,Alexander W.; Pettigrew,Robert M.; Dames,Andrew N.; Howe,Andrew R. L., Position detector.
  739. Ely, David T. E.; Dames, Andrew N., Position sensor.
  740. Ely, David T.; Collins, Ian P.; Cauwood, Peter D.; Brace, Steven R., Position sensor.
  741. Ely, David T. F.; Dames, Andrew N., Position sensor having compact arrangement of coils.
  742. Saylor Michael J. ; Pillsbury Nathan H., Positional-based motion controller with a bias latch.
  743. Scott Paul H. (San Jose CA) Williams Bertrand J. (Campbell CA), Potentiometric oscillator with reset and test input.
  744. Higashiyama Katsuhiko (Neyagawa JPX) Oohama Taizou (Hirakata JPX) Mizoguchi Masahiko (Hirakata JPX) Nishikawa Tsunenari (Sakai JPX), Power control unit protection apparatus.
  745. Parkinson Gerald W. (Shelton CT), Power controller reset during load starting.
  746. Kutz, Harold; Snyder, Warren, Power on reset circuit for a microcontroller.
  747. Magana Javier V., Power on/off control circuit and method.
  748. Barreras ; Sr. Francisco Jose ; Echarri Guillermo ; Echarri Roberto, Power supply having means for extending the operating time of an implantable medical device.
  749. Kutz, Harold; Snyder, Warren, Power supply pump circuit for a microcontroller.
  750. Westwick,Alan L.; Holberg,Douglas R., Precise frequency generation for low duty cycle transceivers using a single crystal oscillator.
  751. Mar, Monte, Precision crystal oscillator circuit used in microcontroller.
  752. Ghosh Subir ; Tung Hsu-Tien, Predictive snooping of cache memory for master-initiated accesses.
  753. van Hook, Timothy J.; Ezer, Gulbin, Preemptive timer multiplexed shared memory access.
  754. Gillespie David ; Allen Timothy P. ; Ferrucci Aaron T., Pressure sensitive scrollbar feature.
  755. Michael A. Angiulo ; Nadim Abdo CA, Procedural toolbar user interface.
  756. Teramoto Yasuhiro,JPX ; Andoh Toshimitsu,JPX ; Isobe Tadaaki,JPX ; Sukegawa Naonobu,JPX ; Ishibashi Yuko,JPX, Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor sha.
  757. Liao, Yuyun; Hameenanttila, Tom M.; Roberts, David B., Processing multiply-accumulate operations in a single cycle.
  758. Johnson William M. (Austin TX) Witt David B. (Austin TX), Processing system for providing an in circuit emulator with processor internal state.
  759. Swoboda Gary L. ; Ehlig Peter N., Processor condition sensing circuits, systems and methods.
  760. Mann Daniel, Processor having a trace access instruction to access on-chip trace memory.
  761. Mann Daniel, Processor including a combined parallel debug and trace port and a serial port.
  762. Bridges Jeffrey Todd ; Green ; III Edward Hammond ; Hofmann Richard Gerard ; Otero David ; Schaffer Mark Michael ; Wilkerson Dennis Charles, Processor local bus posted DMA FlyBy burst transfers.
  763. Wittman Brian Albert, Processor supervisory circuit and method having increased range of power-on reset signal stability.
  764. Tremblay Marc ; O'Connor James Michael ; Joy William N., Processor with accelerated array access bounds checking.
  765. Beck Motti (Tel Aviv ILX) Talmudi Ran (Raanana CA ILX) Iacobovici Sorin (San Jose CA), Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits.
  766. Devins, Robert J.; Ferro, Paul G.; Herzl, Robert D., Processor-independent system-on-chip verification for embedded processor systems.
  767. Asghar Abid (Fair Oaks CA) Donnell James R. (Shingle Springs CA), Product term sharing/allocation in an EPROM array.
  768. Cho Kwang-Bo (Austin), Programmable analog arithmetic circuit for imaging sensor.
  769. Anderson David J. (Scottsdale AZ) Garrity Douglas A. (Gilbert AZ), Programmable analog array and method for configuring the same.
  770. Anderson David J. (Scottsdale AZ) Bersch Danny A. (Gilbert AZ), Programmable analog array and method for establishing a feedback loop therein.
  771. Pierzchala Edmund ; Perkowski Marek A., Programmable analog array circuit.
  772. Mar, Monte, Programmable analog system architecture.
  773. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Altos CA), Programmable application specific integrated circuit and logic cell therefor.
  774. Eric N. Mann ; John Q. Torode, Programmable clock generator.
  775. Mann Eric N. ; Torode John Q., Programmable clock generator.
  776. Mura Joji (Neyagawa JPX) Yabuta Akira (Ashiya JPX) Kitadou Tadaharu (Moriguchi JPX) Kuroda Minoru (Osaka JPX), Programmable controller.
  777. Ueno Kouji (Inagi JPX), Programmable device and method of testing programmable device.
  778. Oshima Hiroyasu,JPX ; Murakoshi Hodaka,JPX ; Nishi Shuji,JPX, Programmable digital circuits.
  779. Atsatt, Sean R.; Jacobs, William S., Programmable display controller.
  780. Piasecki, Douglas S.; Storvik, II, Alvin C., Programmable driver for an I/O pin of an integrated circuit.
  781. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array device having cascaded means for function definition.
  782. Tso Vincent Wing Sing, Programmable highly temperature and supply independent oscillator.
  783. Krokstad Asbjorn (Trondheim NOX) Svean Jarle (Trondheim NOX) Ramstad Tor A. (Saupstad NOX), Programmable hybrid hearing aid with digital signal processing.
  784. Nayak Anup, Programmable interconnect matrix architecture for complex programmable logic device.
  785. Kung Hsiang-Tsung (Pittsburgh PA) Hsu Feng-Hsiung (Pittsburgh PA) Sussman Alan L. (Pittsburgh PA) Nishizawa Teiji (Nara JPX), Programmable interconnection chip for computer system functional modules.
  786. Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.
  787. Kondou Harufusa (Hyogo JPX) Kuranaga Hiroshi (Hyogo JPX), Programmable logic array having a changeable logic structure.
  788. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
  789. Lytle Craig S. ; Faria Donald F., Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
  790. Abbott Curtis, Programmable logic datapath that may be used in a field programmable device.
  791. Lacey, Timothy M.; Johnson, David L., Programmable logic device.
  792. Taylor Brad, Programmable logic device for real time video processing.
  793. Rangasayee Krishna ; Shannon John, Programmable logic device having an integrated phase lock loop.
  794. Hung Lawrence C. (Los Gatos CA) Erickson Charles R. (Fremont CA), Programmable logic device including a parallel input device for loading memory cells.
  795. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
  796. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel, Programmable logic device memory array circuit having combinable single-port memory arrays.
  797. Ong Randy T. (Cupertino CA), Programmable logic device which stores more than one configuration and means for switching configurations.
  798. Craig S. Lytle ; Kerry S. Veenstra, Programmable logic device with highly routable interconnect.
  799. Nishihara Yoshio,JPX, Programmable logic device, information processing system, method of reconfiguring programmable logic device and method compressing circuit information for programmable logic device.
  800. Jefferson David E. ; Cope L. Todd,MYX ; Reddy Srinivas ; Cliff Richard G., Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution.
  801. El-Avat Khaled A. (Cupertino CA) Kaptanoglu Sinan (San Carlos CA) Chan King W. (Los Altos CA) Plants William C. (Santa Clara CA) Lien Jung-Cheun (Santa Clara CA), Programmable logic module and architecture for field programmable gate array device.
  802. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture (mixed analog/digital).
  803. Snyder,Warren; Mar,Monte, Programmable microcontroller architecture (mixed analog/digital).
  804. Hastings Roy A. (Allen TX) Neale Todd M. (Carrollton TX) Whitney Brad (Anaheim CA), Programmable mixed-mode integrated circuit architecture.
  805. Mar Monte F. ; Snyder Warren A., Programmable oscillator scheme.
  806. Li,Gabriel; Chew,Chwei Po; Vecera,Dusan, Programmable phase shift and duty cycle correction circuit and method.
  807. Wojewoda Igor ; Drake Rodney J. ; Boles Brian E., Programmable pin designation for semiconductor devices.
  808. Hsieh Wen-Jai ; Horng Chi-Song ; Wong Chun Chiu Daniel ; Chou Gerchih ; Sathe Shrikant ; Dahlgren Kent, Programmable port for crossbar switch.
  809. Wohl David J. ; Truchsess Joseph F. ; Baytman Alexander L. ; Winslow Robert S., Programmable sound and music making device.
  810. Kean Thomas A.,GBX, Programmable switch for FPGA input/output signals.
  811. Agrawal Om P. ; Sharpe-Geisler Bradley A., Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD.
  812. Distinti Robert J ; Smith Harry F, Programmably interconnected programmable devices.
  813. Gay Donald L., Programmatic use of software debugging to redirect hardware related operations to a hardware simulator.
  814. Mar,Monte; Snyder,Warren, Programming architecture for a programmable analog system.
  815. Chan Victor G., Programming flash in a closed system.
  816. Mar, Monte; Snyder, Warren, Programming methodology and architecture for a programmable analog system.
  817. Wenyi Feng ; William A. Oswald ; Michael L. Roy ; Eric Ting, Programming programmable logic devices using hidden switches.
  818. Snyder, Warren, Protecting access to microcontroller memory blocks.
  819. Yang Yang-Sei,KRX, Prototyping system and a method of operating the same.
  820. Zielinski,Michael R.; Taylor,Michael Jon, Proximity sensor for level sensing.
  821. Volk, Andrew M.; Williams, Michael W., Reading a FIFO in dual clock domains.
  822. Hsu,Louis L.; Mandelman,Jack A.; Wong,Robert C.; Yang,Chih Chao, Real-time adaptive SRAM array for high SEU immunity.
  823. Schneider, Stanley A.; Chen, Vincent W.; Pardo-Castellote, Gerardo; Wang, Howard H.; Joshi, Rajive, Real-time control system development tool.
  824. Hill Charles R. (Peekskill NY) Tyra Fryderyk (Yonkers NY) Akiwumi-Assani Samuel O. (Beacon NY), Real-time tracing of dynamic local data in high level languages in the presence of process context switches.
  825. Lesea Austin H., Realizing analog-to-digital converter on a digital programmable integrated circuit.
  826. Gulati, Kush; Lee, Hae-Seung, Reconfigurable analog-to-digital converter.
  827. Andrade,Hugo A.; Odom,Brian Keith; Ryan,Arthur, Reconfigurable test system.
  828. Ryan Arthur ; Andrade Hugo, Reconfigurable test system.
  829. Pleis,Matthew A.; Sullam,Bert; Lesher,Todd, Reconfigurable testing system and method.
  830. Marantz Joshua D. ; Selvidge Charley ; Crouch Ken ; Seneski Mark E. ; Kudlugi Muralidhar R. ; Stewart William K., Reconstruction engine for a hardware circuit emulator.
  831. Jonathon C. Stiff, Reduced static phase error CMOS PLL charge pump.
  832. Barmak Mansoorian ; Scott Yee TW; Roger Panicacci, Reducing internal bus speed in a bus system without reducing readout rate.
  833. Sudo Naoaki,JPX, Reference voltage generating circuit with MOS transistors having a floating gate.
  834. Dalmia Kamal, Reference-free clock generation and data recovery PLL.
  835. Dalmia Kamal ; Agarwal Anil,INX, Reference-free clock generator and data recovery PLL.
  836. Terzioglu, Esin; Afghahi, Morteza Cyrus; Winograd, Gil I., Refresh techniques for memory data retention.
  837. Green, Michael M., Regenerative signal level converter.
  838. Marik Mark Douglas, Remote program monitor method and system using a system-under-test microcontroller for self-debug.
  839. Mann, Daniel Peter, Remotely accessible integrated debug environment.
  840. Henry Paul D. (Carmel IN) Testin William J. (Indianapolis IN), Reset signal generator, for generating resets of multiple duration.
  841. Arai Makoto (Tokyo JPX), Resume control system and method for executing resume processing while checking operation mode of CPU.
  842. McClannahan, Gary; Nordman, John Emery; Senst, Scott Thomas; Shaffer, John; Youngman, Todd Jason, Reusable configuration tool.
  843. Cheng, Wendy H. W.; Desabilla, Don Rupert S.; Gillespie, David W., Rotary and push type input device.
  844. Ely, David T. E.; Jones, Ross P., Rotary position sensor and transducer for use therein.
  845. Scott Paul H., Roving range control to limit receive PLL frequency of operation.
  846. Joshi,Rajiv V.; Ye,Qiuyi; Chan,Yuen H.; Devgan,Anirudh, Row circuit ring oscillator method for evaluating memory cell performance.
  847. Steele Randy C. (Southlake TX), SRAM based cell for programmable logic devices.
  848. Rosenberg Louis B. (Pleasanton CA) Braun Adam C. (Sunnyvale CA) Schena Bruce M. (Menlo Park CA), Safe and low cost computer peripherals with force feedback for consumer applications.
  849. Michaeli Daniel Reuven, Salad container having insert chamber.
  850. Mead Carver A. (San Jose CA) Allen Timothy P. (Mountain View CA), Scanning method and apparatus for current signals having large dynamic range.
  851. Dunn Robert M. (Woodbridge CT), Schematic diagram generating system using library of general purpose interactively selectable graphic primitives to crea.
  852. Dunn Robert M. (Woodbridge CT), Schematic diagram generating system using library of general purpose interactively selectable graphic primitives to crea.
  853. Doyle James T. (Chandler AZ) Beatty Tim (Mesa AZ) Liepold Carl F. (Mesa AZ), Second order Sigma-Delta based analog to digital converter having superior analog components and having a programmable c.
  854. Hait John N. (Missoula MT), Secure architecture and apparatus using an independent computer cartridge.
  855. Nakano, Hiroo, Security card and a computer system provided with an interface for reading a security card.
  856. Myers Theodore M. ; Palm Richard A. ; Orlando Richard V. ; Adkins Kenneth C., Selectable analog functions on a configurable device and method employing nonvolatile memory.
  857. Comer Donald T. (Los Gatos CA) Dooley Daniel J. (Saratoga CA) Schoeff John A. (Los Gatos CA), Selectable trimming circuit for use with a digital to analog converter.
  858. Sanchez-Frank Alejandra (Austin TX) Sirkin Martin J. (Austin TX), Selecting and locating graphical icon objects to define and configure the workstations in data processing networks.
  859. Johnson Lynn Stewart, Self adapting motor controller.
  860. Olgaard Christian ; Parameswaran Subramanian, Self-adjusting startup control for charge pump current source in phase locked loop.
  861. O\Shaughnessy Timothy G. (Colorado Springs CO) Brown David G. (Pocatello ID), Self-calibrating RC oscillator.
  862. Prazak Paul R. (Tucson AZ) Williams Theodore L. (Tucson AZ), Self-calibrating digital to analog conversion system and method.
  863. Chen, Michael Y.; Brouhard, Michael C.; Wilson, John, Self-describing IP package for enhanced platform based SOC design.
  864. Kitsukawa Goro (Nishitama JPX) Yanagisawa Kazumasa (Kokubunji JPX) Kawahara Takayuki (Kokubunji JPX) Hori Ryoichi (Nishitama JPX) Nakagome Yoshinobu (Hachiouji JPX) Hamma Noriyuki (Kodaira JPX) Itoh , Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier.
  865. Higashino Tohru,JPX, Semiconductor device comprising polysilicon interconnection layers separated by insulation films.
  866. Kiyoshi Fukushima JP, Semiconductor device simulating apparatus and semiconductor test program debugging apparatus using it.
  867. Wachi,Takatsugu; Nakamura,Akira, Semiconductor device, temperature sensor, and electronic apparatus comprising it.
  868. Nakabayashi Takeo (Hyogo JPX), Semiconductor integrated circuit for developing a system using a microprocessor.
  869. Kimura,Yasuyuki; Shimizu,Satoshi; Yokota,Masakatsu; Suyama,Ken; Dec,Aleksander, Semiconductor integrated circuit having built-in PLL circuit.
  870. Terauchi Youji,JPX, Semiconductor integrated circuit incorporating therein clock supply circuit.
  871. Oguchi Yasuhiro,JPX ; Miyayama Yoshiyuki,JPX, Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same.
  872. Fujisawa, Hiroki, Semiconductor memory device and control method.
  873. Adams R. Dean ; Busch Robert E. ; Pilo Harold ; Rudgers George E., Semiconductor memory device having resistive bitline contact testing.
  874. Hong, Sang Hoon; Kim, Si Hong, Semiconductor memory device, and method for testing the same.
  875. Au, Johnie C.; Thakur, Sangeeta, Semiconductor memory self-test controllable at board level using standard interface.
  876. Burch Richard Gene ; Mozumder Purnendu Kanti, Semiconductor structure design and process visualization through the use of simple process models and intuitive interfac.
  877. Mead Carver A. (Pasadena CA) Faggin Federico (Los Altos Hills CA), Sense amplifier.
  878. Mead Carver A. ; Delbruck Tobias, Sense amplifier for high-density imaging array.
  879. Guy J. Farruggia ; Allan B. Fraser, Sensor and sensor system for liquid conductivity, temperature and depth.
  880. Hibbs,Andrew D.; Matthews,Robert, Sensor system for measurement of one or more vector components of an electric field.
  881. Nolan James B. ; Dellacroce Brian, Serial communication interface system having programmable microcontroller for use in a battery pack.
  882. Mueck, Michael; Laing, David Gerrard; Guery, Alain Valentin, Serial interface for an analog to digital converter and a converter including such an interface.
  883. Schneider Thomas R., Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator.
  884. Kubota Yasushi,JPX ; Shiraki Ichiro,JPX, Series connected multi-stage linear FET amplifier circuit.
  885. Pawloski Martin B. (Scottsdale AZ), Shared bus in-circuit emulator system and method.
  886. Gough John J. (Beith Ayrshire GBX), Signal conditioning apparatus and method exhibiting accurate input impedance and gain characteristics over common mode r.
  887. Koifman Vladimir,ILX, Signal converting receiver having constant hysteresis, and method therefor.
  888. Michael Zarubinsky IL; Konstantin Berman IL; Eliav Zipper IL, Signal generator, and method.
  889. Ely, David T.; Dames, Andrew N., Signal processing apparatus and method.
  890. Wong See-Hoi Caesar ; Liu Edward, Signal processing scheme utilizing oversampled switched capacitor filter.
  891. Philipp Harald (Aloha OR), Signal sampling system.
  892. Kidder, Joseph D.; Mahler, Michael B.; Perreault, Edward L.; Stearns, Margaret; Hurley, Jim, Signatures for facilitating hot upgrades of modular software components.
  893. Lin, Hsueh-Tso; Chen, Kuan-Ching, Silicone-polyester-polysilicate hybrid compositions for thermal resistance coating.
  894. Wang Steven ; Tseng Ping-Sheng ; Lin Sharon Sheau-Pyng ; Tsay Ren-Song ; Sun Richard Yachyang ; Shen Quincy Kun-Hsu ; Tsai Mike Mon Yen, Simulation server system and method.
  895. Devins, Robert J.; Kautzman, Mark E.; Mahler, Kenneth A.; Mitchell, William E., Simulator-independent system-on-chip verification methodology.
  896. Shaw Carl, Single chip communication device that implements multiple simultaneous communication channels.
  897. Kawata Kazuhide (Tokyo JPX), Single chip microcomputer capable of debugging an external program without an increase of the number of terminals/ports.
  898. Heene Mark R. (Austin TX) Menkedick Michael H. (Kokomo IN) Sibigtroth James M. (Round Rock TX) Espinor George L. (Austin TX), Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory.
  899. Richmond, Greg; Akyildiz, Ahmet; Shkidt, Alex, Single ended clock signal generator having a differential output.
  900. Ronald D. Malcolm, Jr. ; Jeff Klaas ; Mark Gentry ; Phillip Matthews, Single-chip audio circuitry, method, and systems using the same.
  901. Ahn, Jong-Keun; Yu, Bum-Seok; Ra, Sang-Joo; Kim, Jong-In, Single-chip data processing apparatus incorporating an electrically rewritable nonvolatile memory and method of operating the same.
  902. Tanagawa Kouji (Tokyo JPX) Yoshida Tomoaki (Tokyo JPX), Single-chip microcomputer.
  903. Westwick Alan Lee ; Traylor Kevin Bruce, Single-ended to differential converter.
  904. Mulder, Jan; Lugthart, Marcel; Lin, Chi-Hung, Single-ended-to-differential converter with common-mode voltage control.
  905. Ahuja Bhupendra K. (Fremont CA), Skew-free clock signal distribution network in a microprocessor.
  906. Mann Daniel P. ; Wakeland Carl K., Software debug port for a microprocessor.
  907. Kunst David J., Solid state temperature measurement.
  908. Douglas Robert Petty ; Scott Anthony Sylvester, Specification language for defining user interface panels that are platform-independent.
  909. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Specifying and targeting portions of a graphical program for real-time response.
  910. Heidari Alireza Ryan, Speech recall in cellular telephone.
  911. I-Teh Sha, Spread spectrum at phase lock loop (PLL) feedback path.
  912. Mays Wesley M. ; Kam Siu Aaron J. ; Fontanarosa Mike D., Spread spectrum frequency hopping reader system.
  913. Katsioulas, Athanassios; Chow, Stan; Avidan, Jacob; Fotakis, Dimitris, Standard block architecture for integrated circuit design.
  914. Pascucci Luigi,ITX, Standby voltage boosting stage and method for a memory device.
  915. Henry, G. Glenn; Parks, Terry, Static branch prediction mechanism for conditional branch instructions.
  916. Mo Hyun-Sun,KRX ; Kwak Choong-Keun,KRX, Static random access memory device with burn-in test circuit.
  917. Sorge, Terri L.; Fischer, Kevin J.; Timasheva, Anna V.; Johnson, Russell S.; Misra, Rajeev S.; Niemisto, Juha; Coffen, Robert W.; Natarajan, Ramakrishnan, Storage of application specific data in HTML.
  918. Ogami, Kenneth Y.; Zhaksilikov, Marat, Storing of global parameter defaults and using them over two or more design projects.
  919. Whitten Ralph G. (San Jose CA) Guo Ta-Pen (Cupertino CA) Mohsen Amr (Saratoga CA) Comer Alan E. (San Jose CA), Structures for electrostatic discharge protection of electrical and other components.
  920. Allen Timothy P. ; Schediwy Richard R. ; Faggin Federico, Stylus input capacitive touchpad sensor.
  921. Mead Carver A. (Pasadena CA) Allen Timothy P. (Palo Alto CA), Subthreshold CMOS amplifier with offset adaptation.
  922. Mead Carver A. (Pasadena CA), Subthreshold CMOS amplifier with wide input voltage range.
  923. Snyder,Warren S., Successive approximate capacitance measurement circuit.
  924. Stein Michael Victor (San Jose CA), Supervisory control system for networked multimedia workstations that provides reconfiguration of workstations by remote.
  925. Austin H. Lesea ; Stephen M. Trimberger, Supporting multiple FPGA configuration modes using dedicated on-chip processor.
  926. Crosetto Dario B. (DeSoto TX), Switch for serial or parallel communication networks.
  927. Veneruso John E. (Hurst TX), Switched capacitance automatic meter reading device.
  928. Clark William A., Switched capacitor current source for use in switching regulators.
  929. Philipp Harald (5600 SW. 206th Aloha OR 97007), Switching amplifier circuit.
  930. Ben-Meir Sam (Sharon MA) Gibbons John F. (Natick MA) Thomas Ian (Hopkinton MA), Switching hub intelligent power management.
  931. Kapusta Richard L. ; Chan Caleb, Symmetric logic block input/output scheme.
  932. Mead Carver A. (Pasadena CA) Allen Timothy P. (Palo Alto CA) Faggin Federico (Los Altos Hills CA) Anderson Janeen D. W. (Fremont CA), Synaptic element and array.
  933. Mead Carver A. (Pasadena CA) Faggin Federico (Los Altos Hills CA) Allen Timothy P. (Palo Alto CA) Anderson Janeen D. W. (Femont CA), Synaptic element and array.
  934. Platt John C. (Mountain View) Anderson Janeen D. W. (Fremont) Mead Carver A. (Pasadena CA), Synaptic element including weight-storage and weight-adjustment circuit.
  935. Lee, Soo-Hyoung, Synchronizing circuits and methods for parallel path analog-to-digital converters.
  936. Freidin Philip M. (Sunnyvale CA) Cheung Edmond Y. (San Jose CA) Erickson Charles R. (Fremont CA) Syu Tsung-Lu (Fremont CA), Synchronous dual port RAM.
  937. Konishi Yasuhiro (Hyogo JPX) Miyamoto Takayuki (Hyogo JPX) Kajimoto Takeshi (Hyogo JPX) Iwamoto Hisashi (Hyogo JPX), Synchronous semiconductor memory device.
  938. Wu Chau-Chin ; Tien Ta-Ke ; Fang Wen-Kuan, Synchronous sense amplifier with temperature and voltage compensated translator.
  939. Lee Young-Dae,KRX, Synchronous systems having secondary caches.
  940. Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Tran Giap H. ; Nguyen Bai, Synthesis-friendly FPGA architecture with variable length and variable timing interconnect.
  941. Nemecek, Craig, System and a method for checking lock step consistency between an in circuit emulation and a microcontroller while debugging process is in progress.
  942. Nemecek, Craig, System and a method for communication between an ICE and a production microcontroller while in a halt state.
  943. Chen,Wei; Mair,Hugh T.; Ko,Uming; Scott,David B., System and method for IDDQ measurement in system on a chip (SOC) design.
  944. Omid Sojoodi ; Robert Dye ; Murali Parthasarathy ; Ram Kudukoli, System and method for accessing object capabilities in a graphical program.
  945. Nemecek,Craig; Roe,Steve, System and method for automatically matching components in a debugging system.
  946. Chia Huei Lee ; Jensen Tsai ; Meng-Hui Chen TW; Banghwa Ho TW; Yen-Son Huang ; Changson Teng, System and method for browsing graphically an electronic design based on a hardware description language specification.
  947. Edwards, David Alan; Rich, Anthony Willis, System and method for communicating with an integrated circuit.
  948. Edwards, David Alan; Rich, Anthony Willis, System and method for communicating with an integrated circuit.
  949. Edwards, David Alan; Rich, Anthony Willis; Ramanadin, Bernard, System and method for communicating with an integrated circuit.
  950. Bernardo Elayda, System and method for configuring a programmable logic device.
  951. Peck,Joseph E.; Novacek,Matthew; Andrade,Hugo A.; Petersen,Newton G., System and method for configuring a reconfigurable system.
  952. Barlow Doug ; Dillaway Blair ; Fox Barbara ; Lipscomb Terry ; Spies Terrence, System and method for configuring and managing resources on a multi-purpose integrated circuit card using a personal computer.
  953. Ogami, Kenneth Y.; Pleis, Matthew A., System and method for creating a boot file utilizing a boot template.
  954. Rostoker Michael D. ; Watkins Daniel R., System and method for creating and validating structural description of electronic system from higher-level and behavior.
  955. Ogami, Kenneth Y.; Bartz, Manfred; Anderson, Douglas H., System and method for decoupling and iterating resources associated with a module.
  956. Zeanah James ; Abbott Charles ; Boyd Nik ; Cohen Albert ; Cook James ; Grandcolas Michael ; Lan Sikhun ; Lindsley Bonnie ; Markarian Grigor ; Moss Leslie, System and method for delivering financial services.
  957. Eneboe, Michael; Hamlin, Christopher L., System and method for designing an integrated circuit.
  958. Boylan Jeffrey J. ; Jacobs Mark E. ; Rozman Allen F., System and method for determining output current and converter employing the same.
  959. Welch, M. Jason; Nuber, Paul D, System and method for dynamic modification of integrated circuit functionality.
  960. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
  961. Gerpheide George E. ; Kelliher Jack S. ; Robinson Everett D., System and method for extending the drag function of a computer pointing device.
  962. Cahill-O'Brien, Barry; Cornwall, Mark K., System and method for oscillator self-calibration using AC line frequency.
  963. Westerman, Wayne Carl, System and method for recognizing touch typing under limited tactile feedback conditions.
  964. Schultz Thomas J. ; Campbell Alan J., System and method for remote sensing and receiving.
  965. Glowny David Andrew, System and method for remote software configuration and distribution.
  966. Leibold William Steven, System and method for simulating signal flow through a logic block pattern of a real time process control system.
  967. Tournemille, Jerome; Tamagno, David, System and method for simulating universal serial bus smart card device connected to USB host.
  968. Pauna Mark R., System and method for simulation of integrated hardware and software components.
  969. Bortfeld, Ulrich, System and method for synchronized control of system simulators with multiple processor cores.
  970. Buckmaster Michael R. ; Berger Arnold S., System and method for testing an embedded microprocessor system containing physical and/or simulated hardware.
  971. Ciolfi, John Edward; Mani, Ramamurthy; Orofino, Donald Paul; Shakeri, Mojdeh; Ullman, Marc; Yeddanapudi, Murali, System and method for using execution contexts in block diagram modeling.
  972. Sundararajarao Mohan ; Stephen M. Trimberger, System and method of computation in a programmable logic device using virtual instructions.
  973. Pleis, Matthew A.; Ogami, Kenneth Y.; Snyder, Warren, System and method of dynamically reconfiguring a programmable integrated circuit.
  974. Gove Robert J. ; Balmer Keith,GBX ; Ing-Simmons Nicholas Kerin,GBX ; Guttag Karl Marion, System and method of memory access in apparatus having plural processors and plural memories.
  975. Sullam, Bert; Kutz, Harold, System and method of providing a programmable clock architecture for an advanced microcontroller.
  976. Cseri Istvan, System and methods for building spreadsheet applications.
  977. Liaw Weikuo ; Spencer Percy LeBaron ; Orton David Alan, System and methods for compressing user settings based on default values.
  978. Joseph Michael Ammirato ; Gavin Peacock, System and methods for improved scenario management in an electronic spreadsheet.
  979. Anderson Charles R. (Santa Cruz CA) Warfield Robert W. (Aptos CA) Cseri Istvan (Scotts Valley CA) Low Murray K. (Santa Cruz CA) Liaw Weikuo (Scotts Valley CA) Bush Alan M. (Palo Alto CA), System and methods for improved spreadsheet interface with user-familiar objects.
  980. Anderson Charles R. ; Warfield Robert W. ; Cseri Istvan ; Low Murray K. ; Liaw Weikuo ; Bush Alan M., System and methods for improved spreadsheet interface with user-familiar objects.
  981. Anderson Charles R. ; Warfield Robert W. ; Cseri Istvan ; Low Murray K. ; Liaw Weikuo ; Bush Alan M., System and methods for improved spreadsheet interface with user-familiar objects.
  982. Kato, Takeshi, System comprising host device that determines compatibility of firmware for connected peripheral device and downloads optimum firmware if peripheral device is not compatible.
  983. Nakamura Takeo,JPX ; Kobuchi Eiko,JPX ; Ohtsuka Masato,JPX ; Saitoh Takashi,JPX ; Kobayashi Yukiyasu,JPX ; Kubota Kenichi,JPX, System design/evaluation CAD system and program storage medium.
  984. Shah Tushar (Beaverton OR), System development and debug tools for power management functions in a computer system.
  985. Coker Robert T. (Centerville GA), System for analysis of embedded computer systems.
  986. Amini Nader (Boca Raton FL) Yamauchi Kazushi (Boca Raton FL), System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of periphe.
  987. Taylor,Brian; Layton,Michael D.; Taylor,David, System for disposing a proximity sensitive touchpad behind a mobile phone keypad.
  988. Watkins Daniel (Los Altos CA) Werner Jeffrey A. (Santa Clara CA) Hweizen H. I. (San Jose CA), System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data.
  989. Lynch, Gerard D.; Berenson, Dana Bruce; Woodard, Andrew Shay, System for transferring customized hardware and software settings from one computer to another computer to provide personalized operating environments.
  990. Baker Richard T., System for writing a plurality of data bits less than from the total number of bits in a data register using a single re.
  991. Bell James S. ; Tomlinson Franklin D. ; Wason Michael A., System level functional testing through one or more I/O ports of an assembled computer system.
  992. Faustini, Antony Azio, System, method and article of manufacture for creating an object oriented component having multiple bidirectional ports for use in association with a java application or applet.
  993. Bowen, Matt, System, method and article of manufacture for signal constructs in a programming language capable of programming hardware architectures.
  994. Smayling Michael C. (Missouri City TX), Systems utilizing a single chip microcontroller having non-volatile memory devices and power devices.
  995. MacKenna Craig A. (Los Gatos CA) Dalrymple Monte J. (Fremont CA), Technique for automatically adapting a peripheral integrated circuit for operation with a variety of microprocessor cont.
  996. Bocchino Vincent T., Technique for preconditioning I/Os during reconfiguration.
  997. Ichimaru Kouzo (Kunisaki JPX), Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit.
  998. Lu Hung-Pin,TWX, Temperature compensated frequency generating circuit.
  999. Stecker Johannes,DEX, Temperature independent oscillator.
  1000. Scott,Greg, Temperature stable voltage reference circuit using a metal-silicon Schottky diode for low voltage circuit applications.
  1001. Dias Donald R. (Carrollton TX), Temperature-stabilized oscillator.
  1002. Barch Phillip Thomas ; Wong Robert Bruce ; Rice Stephen James, Test access port.
  1003. Snyder, Warren, Test architecture for microcontroller providing for a serial communication interface.
  1004. Paterson Timothy L. (13416 SE. 187th Pl. Renton WA 98058), Test coverage analyzer.
  1005. Mulholland Sean B. ; Allan James D., Test mode entrance through clocked addresses.
  1006. Chin Richard ; Subramanian Raghu, Test results checking via predictive-reactive emulation.
  1007. Coehlo Paul R. ; Gautho Manuel O. ; Fu Yeh-Chen, Test vector verification system.
  1008. Aronoff Alan P. (Pleasanton CA) Birnkrant Marc S. (Palo Alto CA) Matsushima Osamu (San Jose CA) Sugishita Kyosuke (Kanagawa CA JPX) Oba Hisaharu (Sunnyvale CA) Reddy Katta N. (Milpitas CA) Olsen Rich, Testing and emulation of integrated circuits.
  1009. Nightingale, Andrew Mark, Testing compliance of a device with a bus protocol.
  1010. Watanabe,Takao; Ishihara,Shigenobu, Testing method and testing apparatus.
  1011. Casal Humberto Felipe ; Li Hehching Harry ; Nguyen Trong Duc, Three state phase detector.
  1012. Hwang Jeffrey H., Three-pin buck and four-pin boost converter having open loop output voltage control.
  1013. Duong Khue, Tile-based modular routing resources for high density programmable logic device.
  1014. Philipp Harald, Time domain capacitive field detector.
  1015. Bisset Stephen (Palo Alto CA) Miller Robert J. (Fremont CA) Allen Timothy P. (Los Gatos CA) Steinbach Gunter (Palo Alto CA 4), Touch pad driven handheld computing device.
  1016. Caldwell David W., Touch switch with integral control circuit.
  1017. Caldwell, David W., Touch switch with integral control circuit.
  1018. Caldwell,David W., Touch switch with integral control circuit.
  1019. Gerpheide, George; Taylor, Brian; Lee, Daniel, Touchpad having increased noise rejection, decreased moisture sensitivity, and improved tracking.
  1020. Holehan Steven D., Touchpad overlay with tactile response.
  1021. Mann Daniel, Trace synchronization in a processor.
  1022. Dames, Andrew N.; Ely, David T. E., Transducer and method of manufacture.
  1023. Masters John C., Transformerless electroluminescent lamp driver topology.
  1024. Mallard ; Jr. William C. (Nashua NH), Transmission media driving system.
  1025. Nguyen Cong Dinh, Trimmable circuitry for providing compensation for the temperature coefficients of a voltage controlled crystal-less os.
  1026. Roza Engel (Eindhoven NLX) Van Veenendaal Hendrik G. (Eindhoven NLX), Tunable astable multivibrator with buffer transistors.
  1027. Chambers Mark J. (Plantation FL) Finol Jesus P. (Chandler AZ) Phillips James B. (Plantation FL), Tuning circuit for an RC filter.
  1028. Galler Francis A. (Nolfolk MA) Pflueger Randall J. (Cambridge MA), Tunnel diode voltage reference circuit.
  1029. Platt John C. (Mountain View CA) Anderson Janeen D. W. (Fremont CA), Two layer neural network comprised of neurons with improved input range and input offset.
  1030. David Alan Ackerman ; Scott L. Broutin ; James Kevin Plourde ; George John Przybylek ; John William Stayt, Jr., Two path digital wavelength stabilization.
  1031. Seely Joel ; Malak Robert Leonard ; Allen Timothy Peter ; Schediwy Richard Robert ; Cesarotti William Andrew, Two-layer capacitive touchpad and method of making same.
  1032. Williams Clark R. (Plano TX) Jiang Ching-Lin (Dallas TX), Two-mode oscillator.
  1033. Schutte Herman (Groenewoudseweg 1 Eindhoven NLX), Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both l.
  1034. Moelands Adrianus P. M. M. (Eindhoven NLX) Schutte Herman (Eindhoven NLX), Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations.
  1035. McEwan Thomas E. (Livermore CA), Ultra-wideband directional sampler.
  1036. Thamsirianunt Manop ; Tso Vincent S., Universal duty cycle adjustment circuit.
  1037. Schaffer, Bernhard; Thommen, Daniel; Drenth, Joannes Christianus, Upscaled clock feeds memory to make parallel waves.
  1038. Christensen Reed K. (Hillsboro OR), Use of between-instruction breaks to implement complex in-circuit emulation features.
  1039. Ogami, Kenneth Y.; Roe, Steve, User defined names for registers in memory banks derived from configurations.
  1040. Mitchell Ronald ; Fulton Temple L., User defined port and protocol scheme for a programmable logic controller.
  1041. Livingston, Kris R., User interface apparatus for displaying a range indicator for setting a plurality of target objects.
  1042. Alejandro H. Abdelnur ; Chris Ferris, User interface component.
  1043. Kenney David A. ; Pantone John Anthony ; Wolf Randall K., User interface for graphical application tool.
  1044. Stone Maureen C. ; Bier Eric A. ; DeRose Anthony, User-directed method for operating on an object-based model data structure through a second contextual image.
  1045. Wilkinson,Timothy J.; Guthery,Scott B.; Krishna,Ksheerabdhi; Montgomery,Michael A., Using a high level programming language with a microcontroller.
  1046. Ducaroir Francois ; Nakamura Karl S. ; Jenkins Michael O., Using multiple high speed serial lines to transmit high data rates while compensating for overall skew.
  1047. Johnson Luke A. ; Fiscus Timothy E., Variable delay cell with a self-biasing load.
  1048. Garlepp Bruno Werner ; Chau Pak Shing ; Donnelly Kevin S. ; Portmann Clemenz ; Stark Donald C. ; Sidiropoulos Stefanos ; Yu Leung ; Lau Benedict Chung-Kwong ; Vu Roxanne, Variable delay element.
  1049. Burgan, John M., Variable refresh control for a memory.
  1050. Philipp Harald (4250 W. Lake Sammamish Pkwy. NE. ; #3052 Redmond WA 98052), Variable successive approximation converter.
  1051. Kawamura,Akinobu, Variable-order delta sigma modulator and DA converter.
  1052. Agrawal Om P. (Los Altos CA) Sharpe-Geisler Bradley A. (San Jose CA) Schmitz Nicholas A. (Sunnyvale CA) Moyer Bryon I. (Cupertino CA), Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexib.
  1053. Abramovici Miron, Virtual logic system for reconfigurable hardware.
  1054. Bhaskar Kasi S. (Seattle WA) Peckol James K. (Edmonds WA), Virtual machine programming system.
  1055. Gudaitis Algird M. (Stowe MA), Virtual right leg drive and augmented right leg drive circuits for common mode voltage reduction in ECG and EEG measurem.
  1056. Eiji Ohara JP; Midori Suzuki JP; Shozo Kondo JP; Nobuhiro Suetsugu JP; Akio Hagino JP, Visual programming method and its system.
  1057. Gray Randall C. (Tempe AZ), Voltage clamped differential to single ended converter circuit.
  1058. Mitchell, Eric P.; Gehring, Mark R., Voltage controlled oscillator.
  1059. Moyal Nathan Y., Voltage controlled oscillator (VCO) frequency gain compensation circuit.
  1060. Moyal Nathan Y., Voltage controlled oscillator (VCO) frequency gain compensation circuit.
  1061. May Michael R. (Austin TX), Voltage controlled oscillator (VCO) with symmetrical output and logic gate for use in same.
  1062. Sivadasan,Mohandas Palatholmana; Rohilla,Gajendar, Voltage controlled oscillator delay cell and method.
  1063. Siniscalchi, Patrick Peter, Voltage controlled oscillator having control current compensation.
  1064. Atriss Ahmad H. (Chandler AZ) Peterson Benjamin C. (Tempe AZ) Parker Lanny L. (Mesa AZ), Voltage controlled oscillator operating with digital controlled loads in a phase lock loop.
  1065. Suarez Jose I. (Coral Gables FL), Voltage controlled oscillator with current control.
  1066. Ken Takeuchi JP; Tomoharu Tanaka JP, Voltage generator for compensating for temperature dependency of memory cell current.
  1067. Lee Bang-Wan (Kyungmung-city KRX) Bae Yl-Sung (Seoul KRX), Voltage regulator for generating a constant reference voltage which does not change over time or with change in temperat.
  1068. Caser Fabio Tassan,ITX ; Schippers Stefan,ITX ; Cane Marcello,ITX, Voltage regulator for semiconductor non-volatile electrically programmable memory device.
  1069. Nagahama Yasuo (Hamamatsu JA), Voltage-controlled type oscillator.
  1070. Wenstrand,John S.; Hamilton,Bruce, Wake-up detection method and apparatus embodying the same.
  1071. Philipp Harald (Beaverton OR), Waveform acquisition circuit.
  1072. Weiss, Mitchell, Web based tool control in a semiconductor fabrication facility.
  1073. Dasgupta, Uday; Hwee, Teo Tian, Wide-band single-ended to differential converter in CMOS technology.
  1074. Heile Francis B. ; Fairbanks Brent A., Work group computing for electronic design automation.
  1075. Allen Timothy P. (Los Gatos CA) Greenblatt Adam K. (San Jose CA) Mead Carver A. (Pasadena CA) Anderson Janeen D. W. (Fremont CA), Writable analog reference voltage storage device.
  1076. Allen Timothy P. (Los Gatos CA) Greenblatt Adam K. (San Jose CA) Mead Carver A. (Pasadena CA) Anderson Janeen D. W. (Fremont CA), Writable analog reference voltage storage device.
  1077. LeMoncheck John (El Granada CA) Allen Timothy P. (Los Gatos CA) Steinbach Gunter (Palo Alto CA) Mead Carver A. (Pasadena CA), Writable analog reference voltage storage device.
  1078. LeMoncheck John (El Granada CA) Allen Timothy P. (Los Gatos CA) Steinbach Gunter (Palo Alto CA) Mead Carver A. (Pasadena CA), Writable analog reference voltage storage device.
  1079. Watt Simon C. (Cambridge GBX), Write request interlock.
  1080. Brooke, David M.; Saxon, Steve M., XML server pages language.

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