Methods and apparatus for interfacing between a host processor and a coprocessor
IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0542092
(2006-09-29)
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등록번호 |
US-8095699
(2012-01-10)
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발명자
/ 주소 |
- Garg, Sachin
- Krivacek, Paul D.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
4 인용 특허 :
10 |
초록
▼
An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation
An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.
대표청구항
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1. An interface adapted to transfer data between a host processor and an external coprocessor, the interface comprising: a master-side interface implemented on the host processor;a slave-side interface implemented on the coprocessor, the master-side interface configured to transfer information to an
1. An interface adapted to transfer data between a host processor and an external coprocessor, the interface comprising: a master-side interface implemented on the host processor;a slave-side interface implemented on the coprocessor, the master-side interface configured to transfer information to and from a host processor bus internal to the host processor and the slave-side interface, the slave-side interface configured to transfer information to and from the master-side interface and a coprocessor bus internal to the coprocessor, and the interface adapted to perform a first read operation initiated by the master-side interface and a second read operation initiated by the slave-side interface;a first master-side synchronization component adapted to synchronize transfer of data to and from the host processor bus and a first master-side read buffer that stores read addresses and associated read data for use during the first read operation; anda second master-side synchronization component adapted to synchronize transfer of data to and from the first master-side read buffer and the slave-side interface, and to synchronize transfer of data from the slave-side interface to the second master-side read buffer that stores read data for use during the second read operation;a master-side write buffer configured to store a plurality of write addresses associated with locations on the coprocessor and to store write data to be written to the plurality of write addresses,a slave-side write buffer configured to store the write addresses and the write data;a plurality of physical lines for electrically connecting the host processor to the coprocessor over which the write addresses and write data may be transferred,wherein the second master-side synchronization component is adapted to transfer data from the master-side write buffer to the plurality of physical lines according to an interface clock shared by the master-side interface and the slave-side interface, the second master-side synchronization component configured to transfer a write address stored in the master-side write buffer to the plurality of physical lines on a first clock cycle of a write operation and to transfer associated write data stored in the write buffer to the plurality of physical lines on a second clock cycle of the write operation when in a first write mode, and the second master-side synchronization component configured to transfer the write data stored in the master-side write buffer to the plurality of physical lines on the first clock cycle when in a second write mode. 2. The interface of claim 1, wherein the second slave-side synchronization component is adapted to transfer data from the plurality of external lines to the write buffer according to the interface clock, the second slave-side synchronization component configured to transfer the write address received from the plurality of physical lines to the slave-side write buffer on the first clock cycle of the write operation and to transfer the associated write data received from the plurality of physical lines to the write buffer on the second clock cycle of the write operation when in the first write mode, and the second slave-side synchronization component configured to transfer the write data received from the plurality of physical connections to the slave-side write buffer on the first clock cycle when in the second write mode. 3. The interface of claim 2, further comprising a write control signal having a plurality of states, the plurality of states indicating whether the interface is operating in the first write mode or the second write mode. 4. The interface of claim 3, further comprising: a master-side address register to store a last write address transferred over the plurality of physical lines; anda slave-side address register to store the last write address. 5. The interface of claim 1, wherein a number of the plurality of physical lines is equal to a number of bits in each of the plurality of write addresses. 6. The interface of claim 1, further comprising: a plurality of master-side buffers including the master-side write buffer, the first master-side read buffer and the second master-side read buffer;a first clock signal to synchronize transfers of data to and from the host processor bus and at least some of the plurality of master-side buffers; anda second clock signal to synchronize transfers of data to and from at least some of the plurality of master-side buffers and the slave-side interface; anda plurality of master-side clock gates each associated with a respective one of the plurality of master-side buffers, each of the plurality of clock gates adapted to gate off at least one of the first clock signal and the second clock signal when the respective one of the plurality of master-side buffers is not in use. 7. The interface of claim 6, further comprising: a plurality of slave-side buffers including the slave-side write buffer, the first slave-side read buffer and the second slave-side read buffer, wherein the second clock signal synchronizes transfer of data to and from the master-side interface and at least some of the plurality of slave-side buffers;a third clock signal synchronizing transfer of data to and from at least some of the plurality of slave-side buffers and the coprocessor bus; anda plurality of slave-side clock gates each associated with a respective one of the plurality of slave-side buffers, each of the plurality of slave-side clock gates adapted to gate off at least one of the second clock signal and third clock signal when the respective one of the plurality of slave-side buffers is not in use. 8. The interface of claim 7, wherein the plurality of master-side clock gates include at least two master-side clock gates for each of the plurality of master-side buffers, a first of the at least two master-side clock gates for each of the plurality of master-side buffers configured to gate off the first clock signal and a second of the at least two master-side clock gates for each of the plurality of master-side buffers configured to gate off the second clock signal, and wherein the plurality of master-side clock gates are configured to independently and automatically gate off the respective clocks to the respective ones of the plurality of master-side buffers when the respective buffer is empty. 9. The interface of claim 8, wherein the plurality of slave-side clock gates include at least two slave-side clock gates for each of the plurality of slave-side buffers, a first of the at least two slave-side clock gates for each of the plurality of slave-side buffers configured to gate off the first clock signal and a second of the at least two slave-side clock gates for each of the plurality of slave-side buffers configured to gate off the second clock signal, and wherein the plurality of slave-side clock gates are configured to independently and automatically gate off the respective clocks to the respective ones of the plurality of slave-side buffers when the respective buffer is empty. 10. The interface of claim 9, further comprising a global clock gate configured to gate off the first clock signal and the second clock signal from each of plurality of master-side buffers and each of the plurality of slave-side buffers. 11. The interface of claim 10, wherein the global clock gate can be activated and deactivated by a control signal, the global clock gate being activated when none of the plurality of buffers are in use. 12. The interface of claim 1, further comprising a priority register to store a value indicating one of a plurality of priority schemes controlling the order in which the second master-side synchronization component transfers write information from the master-side write buffer to the slave-side write buffer and read information from the first master-side read buffer to the first slave-side read buffer over the plurality of physical lines when more than one of write information and read information is available to transfer.
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