초록 ▼

The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element (424) between a first and a second metal

The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element (424) between a first and a second metal structure. The fabrication comprises providing an ambient environment adjacent to an interconnect surface region of a substrate that is suitable for allowing growth of at least one metal dendrite between the first and second metal structures, and initiating and sustaining self-assembly of a metal structure comprising at least one metal dendrite in the interconnect surface region between the first and second metal structures by irradiating the pn junction with photons of an energy suitable for creating free charge carriers in the first and second doped substrate regions and thus creating an electric potential difference between the first and second metal structures, which is suitable for electrolysis of metal from at least one of the first and second metal structures.

대표청구항 ▼

1. A method for fabricating an interconnect element on a substrate surface between a first metal structure and a second metal structure, comprising the steps of providing a semiconductor substrate with a pn junction formed by a first doped substrate region of a first conductivity type, and a second

1. A method for fabricating an interconnect element on a substrate surface between a first metal structure and a second metal structure, comprising the steps of providing a semiconductor substrate with a pn junction formed by a first doped substrate region of a first conductivity type, and a second doped substrate region of an opposite second conductivity type;fabricating a layer structure on the semiconductor substrate, the layer structure comprising the first metal structure, which is conductively connected with the first doped substrate region, and further comprising the second metal structure, which is conductively connected with the second doped substrate region, the layer structure allowing transmission of photons with an energy suitable for creating free charge carriers in the first and second doped substrate regions;defining an interconnect surface region on the layer structure, which connects the first and second metal structures and which is designated for self-assembly of the metal interconnect element;providing an ambient environment adjacent to the interconnect surface region and suitable for allowing growth of at least one metal dendrite between the first and second metal structures;initiating and sustaining self-assembly of a third metal structure comprising at least one metal dendrite in the interconnect surface region between the first and second metal structures until the third metal structure forms the desired interconnect element, by irradiating the pn junction with photons of an energy suitable for creating free charge carriers in the first and second doped substrate regions and thus creating an electric potential difference between the first and second metal structures, which is suitable for electrolysis of metal from at least one of the first and second metal structures. 2. The method of claim 1, wherein the step of defining the interconnect surface region comprises fabricating a passivation layer on a surface of the layer structure except for the interconnect surface region, the passivation layer being suitable for avoiding growth of metal dendrites. 3. The method of claim 1, wherein the step of defining the interconnect surface region comprises fabricating a resist layer and selectively removing the resist layer only in the desired interconnect surface region. 4. The method of claim 1, wherein the step of defining the interconnect surface region comprises fabricating a surface coating that covers only the interconnect surface region, the surface coating being suitable for stimulating self-assembly of the at least one metal dendrite. 5. The method of claim 4, wherein the step of defining the interconnect surface region comprises removing the resist layer before the step of initiating and sustaining. 6. The method of claim 1, wherein the step of defining the interconnect surface region comprises etching a trench in the interconnect surface regionfabricating a trench liner on a bottom face of the trench, the trench liner being suitable for preventing penetration of the metal of the first and second metal structures. 7. The method of claim 4, wherein a step of mechanical electrical polishing is performed after the self-assembly of the at least one metal dendrite in the trench. 8. The method of claim 1, wherein the step of providing an ambient environment comprises bringing the interconnect surface region in contact with an aqueous ambient environment. 9. The method of claim 1, wherein the step of providing an ambient environment comprises bringing the interconnect surface region in contact with a solution of a metal. 10. The method of claim 1, wherein the step of providing an ambient environment comprises bringing the interconnect surface region in contact with an ambient environment that has a first humidity level, and a step of adjusting to a second humidity level. 11. The method of claim 1, wherein, before the step of defining the interconnect surface region, a step of incorporating metallic contamination into dielectric material extending between the first and second metal structures is performed, and wherein a step of removing the metallic contamination is performed after formation of the interconnect element. 12. The method of claim 1, wherein the step of initiating and sustaining self-assembly of the third metal structure comprises electrically charging either the first or the second or the first and the second metal structures.