초록 ▼

The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOX) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric struct

The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOX) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the layer provides the functionality of a thinner silicon dioxide layer, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.

대표청구항 ▼

1. A capacitor comprising: a first conductive layer;an amorphous dielectric layer disposed on the first conductive layer in an integrated circuit, the amorphous dielectric layer comprising a titanium oxide film doped with from 10 to 30 atomic percent of a lanthanide material selected from the list i

1. A capacitor comprising: a first conductive layer;an amorphous dielectric layer disposed on the first conductive layer in an integrated circuit, the amorphous dielectric layer comprising a titanium oxide film doped with from 10 to 30 atomic percent of a lanthanide material selected from the list including samarium, europium, gadolinium, holmium, erbium and thulium having a dielectric constant of from 50 to 100, the lanthanide doped titanium oxide containing two different lanthanides such that at least one of the two different lanthanides is structured as a lanthanide oxide; anda second conductive layer disposed on the dielectric layer, the second conductive layer and/or the first conductive layer contacting the amorphous dielectric layer. 2. The capacitor of claim 1, wherein the amorphous dielectric layer has a root mean square surface roughness of less than 10 angstroms and a current leakage rate of less than 2×10−7 amps per cm2 at an electric field strength of 1 megavolt per cm. 3. The capacitor of claim 1, wherein the amorphous dielectric layer has an equivalent oxide thickness of less than 10 Angstroms, and a breakdown voltage of greater than 2.5 MV/cm. 4. An electronic device comprising: a dielectric layer containing a layer of lanthanide doped titanium oxide in an integrated circuit, the lanthanide doped titanium oxide containing two different lanthanides such that at least one of the two different lanthanides is structured as a lanthanide oxide; anda conductive layer contacting the dielectric layer. 5. The electronic device of claim 4 wherein the lanthanide doped titanium oxide layer comprises an amorphous layer. 6. The electronic device of claim 4 wherein the lanthanide doped titanium oxide layer comprises at least two layers of titanium oxide and at least one layer of a lanthanide oxide selected from the list comprising at least one of samarium, europium, gadolinium, holmium, erbium and thulium oxide disposed between the at least two layers of titanium oxide in an integrated circuit. 7. The electronic device of claim 4, wherein the electronic device includes a memory having the dielectric layer as a gate insulator in a transistor device, where the composition of the lanthanides is at least 10% by atomic percent of the dielectric film. 8. An electronic system comprising: a controller;an electronic device coupled to the controller, wherein the electronic device includes: a dielectric layer comprising a lanthanide doped titanium oxide in an integrated circuit and a dielectric constant of from 50 to 100, the lanthanide doped titanium oxide containing two different lanthanides such that at least one of the two different lanthanides is structured as a lanthanide oxide; anda conductive layer contacting the dielectric layer. 9. The electronic system of claim 8, wherein the dielectric layer comprises an amorphous dielectric material, the two different lanthanides selected from the list including samarium, europium, gadolinium, holmium, erbium and thulium. 10. The electronic system of claim 8, wherein the dielectric layer includes at least one amorphous material having a vertical thickness of a single molecular layer formed by atomic layer deposition of a titanium oxide, at least one amorphous material having a vertical thickness of a single molecular layer formed by atomic layer deposition of a lanthanide oxide, and at least one amorphous material having a vertical thickness of a single molecular layer formed by atomic layer deposition of a second titanium oxide. 11. A transistor comprising: a semiconductor substrate;a dielectric layer disposed on the semiconductor substrate having a vertical thickness of less than 100 Angstroms, a dielectric constant of greater than 30, and a breakdown voltage of greater than 2.5 MV/cm, the dielectric layer containing lanthanide doped titanium oxide, the lanthanide doped titanium oxide containing two different lanthanides such that at least one of the two different lanthanides is structured as a lanthanide oxide; anda conductive layer disposed on the dielectric layer. 12. The transistor of claim 11, wherein the dielectric layer includes an amorphous nature and includes at least one metal from column IVA of the periodic table, the dielectric layer having a silicon dioxide equivalent thickness of less than 10 Angstroms. 13. The transistor of claim 12, wherein the dielectric layer comprises zirconium. 14. The transistor of claim 13, wherein the dielectric layer has a root mean square surface roughness of less than 10 Angstroms and a current leakage rate of 1.0×10−8 to 2×10−7 amps per cm2 at an electric field strength of 1.0 to 2.0 megavolt per cm. 15. The transistor of claim 14, wherein the dielectric layer comprises a nano-laminated dielectric layer. 16. The transistor of claim 15, wherein one of the first plurality of layers directly contacts the semiconductor substrate. 17. The transistor of claim 16, wherein the first plurality of layers each have a thickness of 0.12 nm. 18. An electronic device comprising: a dielectric layer containing a layer of lanthanide doped TiO2 in an integrated circuit, the lanthanide doped TiO2 containing two different lanthanides such that at least one of the two different lanthanides is structured as a lanthanide oxide; anda conductive layer contacting the dielectric layer. 19. The electronic device of claim 18, wherein the dielectric layer is structured as a nanolaminate. 20. The electronic device of claim 19, wherein the integrated circuit includes a NROM flash memory device.