초록 ▼

A multi-stage missile with plural stages adapted to be physically coupled to and decoupled from adjacent stages and a processor disposed on a single stage for controlling each stage thereof. In the illustrative embodiment, the processor includes a field programmable gate array. In the illustrative e

A multi-stage missile with plural stages adapted to be physically coupled to and decoupled from adjacent stages and a processor disposed on a single stage for controlling each stage thereof. In the illustrative embodiment, the processor includes a field programmable gate array. In the illustrative embodiment, the processor is disposed on stage 4 of a four-stage missile and performs guidance and navigation functions for each stage and control functions for stages 2, 3 and 4. In a specific embodiment, a serial bus interface is included for coupling the processor to electronic circuitry on each of the stages of the missile. In the best mode, the interface is an IEEE 1394b interface with a physical layer interface and a link layer interface.

대표청구항 ▼

1. A digital interface unit (DIU) configured to be disposed on a final stage of a multi-stage missile, the DIU comprising: a gate array having plural ports, interfaces and interface logic circuits for interconnecting and disconnecting multiple processors;a first processor coupled to the gate array;

1. A digital interface unit (DIU) configured to be disposed on a final stage of a multi-stage missile, the DIU comprising: a gate array having plural ports, interfaces and interface logic circuits for interconnecting and disconnecting multiple processors;a first processor coupled to the gate array; anda second processor coupled to the first processor via the gate array,wherein the DIU is configured to perform guidance and navigation functions for each of the stages of the multi-stage missile and control functions for only some of the stages through a serial bus interface that provides a daisy-chain interconnection between the stages,wherein at least one of the processors is a guidance processor that is configured with stage-control instructions to perform the guidance and navigation functions of the stages,wherein the gate array is a field programmable gate array (FPGA) to configure the guidance processor with the stage-control instructions for a currently-controlled stage,wherein the guidance processor is configured to execute stage-control instructions for the currently-controlled stage prior to separation of the currently-controlled stage,wherein the DIU is configured to order stage separation and provide a stage-gone signal to the guidance processor, andwherein the stage-control instructions are configured to check for the presence of the stage-gone signal and cause the FPGA to configure the guidance processor with stage-control instructions for controlling a next stage in response thereto. 2. A multi-stage missile comprising a plurality of stages adapted to be physically coupled to and decoupled from adjacent stages, the missile comprising: a digital interface unit (DIU) disposed on a final stage configured to perform guidance and navigation functions for each of the stages and control functions for only some of the stages; anda serial bus interface to couple the DIU to electronic circuitry on each of the stages, the serial bus interface to provide a daisy-chain interconnection between the stages,wherein the DIU includes: a guidance processor configured with stage-control instructions to perform the guidance and navigation functions of the stages;a field programmable gate array (FPGA) to configure the guidance processor with the stage-control instructions for a currently-controlled stage; anda bus controller configured to control the serial bus interface,wherein the guidance processor is configured to execute stage-control instructions for the currently-controlled stage prior to separation of the currently-controlled stage. 3. The multi-stage missile of claim 2 wherein the DIU is configured to order stage separation and provide a stage-gone signal to the guidance processor, and wherein the stage-control instructions are configured to check for the presence of the stage-gone signal and cause the FPGA to configure the guidance processor with stage-control instructions for controlling a next stage in response thereto. 4. The multi-stage missile of claim 3 wherein the final stage is a fourth stage, and wherein the multi-stage missile includes first, second and third stages, wherein the fourth stage includes a payload,wherein the third stage includes a third stage controller to receive guidance, navigation and autopilot commands from the DIU through the serial bus interface and to provide thrust vector and attitude control signals in response thereto, andwherein the third stage controller is coupled to electrically activated explosive devices, a power conditioning unit (PCU) and input/output (I/O) interface, wherein the I/O interface is to receive vehicle location data from an onboard GPS receiver and communicate with the DIU via the serial bus interface, the I/O interface and the serial bus interface being configured to allow GPS, guidance, attitude control and other stage-related data to be forwarded to the DIU to allow the DIU to trigger an ejection of the third stage by activating the electrical explosive devices. 5. The multi-stage missile of claim 4 wherein the second stage includes a second stage electronics package coupled to the DIU via the serial bus interface, the second stage including an IMU, a second stage linear shaped charge (LSC) for mechanical separation of the second stage, and an I/O controller to collect telemetry and IMU data to be forwarded to the DIU over the serial bus to allow the DIU to trigger an ejection of the second stage. 6. The multi-stage missile of claim 5 wherein the first stage includes a first stage electronics package including a thrust vector controller (TVC), TVC drivers, separation ordinance and a first stage LSC for mechanical separation of the first stage, the first stage being coupled to the DIU via the serial bus interface to allow the DIU to trigger an ejection of the first stage. 7. The multi-stage missile of claim 6 wherein the DIU is configured to perform guidance and navigation functions for the first, second, third and fourth stages based on stage-control instructions for an associated stage, and wherein the DIU is configured to perform control functions for only the second, third and fourth stages based on stage-control instructions for an associated stage. 8. The multi-stage missile of claim 2 wherein the serial bus interface is an IEEE 1394b configured interface with a physical layer interface and a link layer interface. 9. A method for controlling a plurality of stages of multi-stage missile, the plurality of stages adapted to be physically coupled to and decoupled from adjacent stages, the method comprising: performing guidance and navigation functions for each of the stages and control functions for only some of the stages with a digital interface unit (DIU) disposed on a final stage; andproviding a daisy-chain interconnection between the stages with a serial bus interface that couples the DIU to electronic circuitry on each of the stages,wherein the method includes:configuring a guidance processor with stage-control instructions to perform the guidance and navigation functions of the stages using a field programmable gate array (FPGA) that configures the guidance processor with the stage-control instructions for a currently-controlled stage; andexecuting stage-control instructions for the currently-controlled stage prior to separation of the currently-controlled stage. 10. The method of claim 9 further comprising configuring the DUI to order stage separation and provide a stage-gone signal to the guidance processor, and wherein the stage-control instructions are configured to check for the presence of the stage-gone signal and cause the FPGA to configure the guidance processor with stage-control instructions for controlling a next stage in response thereto.