IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0173899
(2008-07-16)
|
등록번호 |
US-8105936
(2012-01-31)
|
발명자
/ 주소 |
- Yang, Chih-Chao
- Hsu, Louis C.
- Joshi, Rajiv V.
|
출원인 / 주소 |
- International Business Machines Corporation
|
대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
20 |
초록
▼
Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielec
Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma. Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may be provided along an interface between the via and an internal metal layer.
대표청구항
▼
1. A method for fabricating a dielectric interconnect structure, comprising: providing an interconnect structure having an exposed dielectric layer;depositing a glue layer on the exposed dielectric layer;removing the glue layer from at least one horizontal surface of the exposed dielectric layer;cre
1. A method for fabricating a dielectric interconnect structure, comprising: providing an interconnect structure having an exposed dielectric layer;depositing a glue layer on the exposed dielectric layer;removing the glue layer from at least one horizontal surface of the exposed dielectric layer;creating a modified dielectric surface by treating the exposed dielectric layer with a gaseous ion plasma after the removing of the glue layer from the at least one horizontal surface of the exposed dielectric layer; anddepositing a noble metal layer directly on the modified dielectric surface. 2. The method of claim 1, the noble metal being layer selected from a group consisting of Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa. 3. The method of claim 1, the gaseous ion plasma being selected from a group consisting of Ar, He, Ne, Xe, N2, H2, NH3, and N2H2. 4. The method of claim 1, the providing comprising post etching in the interconnect structure to form at least one trench and at least one via in the exposed dielectric layer. 5. The method of claim 4, the noble metal layer lacking along a bottom surface of the at least one via. 6. The method of claim 4, further comprising: filling the at least one trench and at least one via with conductive material; andperforming chemical mechanical polishing after the filling of the at least one trench and the at least one via with conductive material. 7. A method for fabricating a dielectric interconnect structure, comprising: providing an interconnect structure having an exposed dielectric layer;depositing a glue layer on the exposed dielectric layer, the glue layer comprising TaN;removing the glue layer from at least one horizontal surface of the exposed dielectric layer;creating a modified dielectric surface by treating the exposed dielectric layer with a gaseous ion plasma after the removing of the glue layer from the at least one horizontal surface of the exposed dielectric layer; anddepositing a noble metal layer directly on the modified dielectric surface. 8. The method of claim 7, the noble metal being layer selected from a group consisting of Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa. 9. The method of claim 7, the gaseous ion plasma being selected from a group consisting of Ar, He, Ne, Xe, N2, H2, NH3, and N2H2. 10. The method of claim 7, the providing comprising post etching in the interconnect structure to form at least one trench and at least one via in the exposed dielectric layer. 11. The method of claim 10, the noble metal layer lacking along a bottom surface of the at least one via. 12. The method of claim 10, further comprising: filling the at least one trench and at least one via with conductive material; andperforming chemical mechanical polishing after the filling of the at least one trench and the at least one via with conductive material.
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