IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0438125
(2006-05-18)
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등록번호 |
US-RE43112
(2012-01-17)
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발명자
/ 주소 |
- Corisis, David J.
- Brooks, Jerry M.
- Moden, Walter L.
|
출원인 / 주소 |
|
대리인 / 주소 |
Lerner, David, Littenberg, Krumholz & Mentlik, LLP
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인용정보 |
피인용 횟수 :
1 인용 특허 :
171 |
초록
▼
A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including t
A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.
대표청구항
▼
1. A computer system having an input device, an output device, a processor connected to said input device and said output device, and a memory connected to said processor, comprising: said memory comprising a memory module connected to said processor, said memory module including: a ball grid array,
1. A computer system having an input device, an output device, a processor connected to said input device and said output device, and a memory connected to said processor, comprising: said memory comprising a memory module connected to said processor, said memory module including: a ball grid array, comprising: a printed circuit board substrate having a first surface, a second surface, and an aperture, said first surface including a plurality of conductive element pads, at least one conductive element pad on said second surface and at least one terminal pad on said second surface;a memory semiconductor device-mounted within a first perimeter of said first surface of said printed circuit board substrate and having at least one bond pad;at least one wire bond connected to said at least one bond pad on said memory semiconductor device and said at least one terminal pad on said second surface of said printed circuit board substrate while passing through said aperture;a material placed along said aperture, on said at least one bond pad, said at least one terminal pad, and said at least one wire bond, forming a first profile height; anda plurality of conductive elements, mounted along a second perimeter of said second surface, said second perimeter being greater than said first perimeter, and coupled to said at least one conductive element pad on said second surface, said plurality of conductive elements having a second profile height greater than said first profile height. 2. The computer system according to claim 1, wherein a first part of each conductive element of said plurality of conductive elements aligns in a first parallel row having a first pitch spacing. 3. The computer system according to claim 2, wherein a second part of each conductive element of said plurality of conductive elements aligns in a second parallel row having a second pitch spacing. 4. The computer system according to claim 1, wherein said material has a second profile height less than said first profile height. 5. The computer system according to claim 1, wherein said at least one conductive element pad is connected to said at least one bond pad through said printed circuit board substrate. 6. The computer system according to claim 1, wherein at least one conductive element of said plurality of conductive elements is isolated. 7. A method of forming a stacked semiconductor assembly, comprising: providing a plurality of semiconductor substrates each having a first surface, a second surface, at least one aperture, a plurality of terminal pads on the second surface adjacent the at least one aperture, the terminal pads coupled to conductive element pads on the second surface by conductive traces on the second surface, and a plurality of conductive element pads on the second surface;mounting a respective semiconductor die having a perimeter on the first surface of each of the semiconductor substrates, the semiconductor dies having bond pads on a front surface disposed on the first surface of the respective substrates, the bond pads overlying the at least one aperture in the respective substrates;connecting at least one bond pad of each of the semiconductor dies to at least one of the conductive element pads on the second surface of the respective substrate by connecting one end of a bond wire to a bond pad, extending the bond wire through the at least one aperture, and connecting the opposite end of the bond wire to one of the terminal pads on the second surface on the respective substrates;covering the bond wires and the portion of the semiconductor dies overlying the at least one aperture of each substrate with an encapsulant material, the encapsulant material being disposed in the aperture and projecting beyond the second surface of the respective semiconductor substrate at a first profile height;providing a plurality of conductive elements mounted on the conductive element pads on the second surface of each substrate, the conductive element pads forming a second perimeter on the substrate that is greater than a first perimeter, the conductive elements having a second profile height with respect to the second surface of the respective substrate that is greater than the first profile height, wherein the encapsulant material at the first profile height projects beyond the second surface of the semiconductor substrate such that the encapsulant material is substantially colinear with pairs of the conductive elements that are aligned with a central portion of the second perimeter; andaligning each of the semiconductor substrates in the plurality and positioning the substrates one atop the other such that the conductive elements mounted on the second surface of a first semiconductor substrate of the plurality aligns with and couples to the conductive element pads on the first surface of a second semiconductor substrate of the plurality of substrates, to form a vertically stacked assembly. 8. The method of forming the stacked semiconductor assembly of claim 7, wherein providing a plurality of conductive elements further comprises providing solder balls. 9. The method of forming the stacked semiconductor assembly of claim 7, wherein mounting a semiconductor die further comprises forming a die attach pad on the first surface of each of the plurality of semiconductor substrates for receiving the respective semiconductor die. 10. The method of claim 9, wherein forming a die attach pad further comprises forming an epoxy layer that is a dielectric. 11. The method of claim 9, wherein forming a die attach pad further comprises forming a layer of adhesive and tape wherein the tape is a dielectric. 12. The method of claim 11, wherein providing the tape further comprises providing a tape with an aperture that aligns with the aperture in the substrate. 13. The method of claim 7, wherein mounting the semiconductor dies further comprises providing, for at least one of the semiconductor dies, a memory device. 14. The method of claim 13, wherein mounting the semiconductor dies comprises mounting at least one dynamic memory device. 15. The method of claim 13, wherein mounting a semiconductor die comprises mounting at least one EPROM device. 16. The method of claim 15, wherein mounting an EPROM device comprises mounting a FLASH device. 17. The method of claim 7, wherein mounting the semiconductor dies comprises providing a memory device for each of the semiconductor dies. 18. The method of claim 7, wherein mounting the semiconductor dies further comprises providing semiconductor dies having bond pads located in the center portion. 19. The method of claim 18, wherein providing the substrates with an aperture comprises providing a substrate with a centrally located aperture. 20. The method of claim 7, wherein providing the substrates with an aperture comprises providing a substrate with a centrally located aperture. 21. A method of forming a substrate for use in a stacked semiconductor ball grid array assembly, comprising: providing a substrate having a first surface, a second surface, and an aperture, providing a plurality of conductive element pads on the first and second surfaces, providing terminal pads located adjacent the aperture on the second surface, providing conductive traces located on the second surface and electrically coupled to at least one of the terminal pads and to at least one of the conductive elements pads, and providing conductive vias extending through the substrate and coupling at least one of the conductive element pads on the first surface to at least one of the conductive element pads on the second surface;disposing a semiconductor die on the first surface of the substrate, the semiconductor die having a perimeter that is less than the perimeter on the first surface, the semiconductor die having bond pads that are placed over the aperture;disposing conductive elements on a perimeter on at least some of the conductive element pads on the second surface and electrically coupling these conductive elements to at least some of the conductive element pads on the first surface through the conductive vias, the conductive elements having a conductive element profile height with respect to the second surface;connecting the bond pads of the semiconductor die to at least one of the terminal pads on the second surface of the substrate by connecting a first end of a bond wire to at least one of the bond pads, extending the bond wire through the aperture, and coupling a second end of the bond wire to at least one of the terminal pads; anddisposing encapsulant material over the second surface of the substrate and in the aperture such that the encapsulant material covers the bond wires and a portion of the semiconductor die exposed by the aperture, the encapsulant material projecting beyond the second surface of the substrate at an encapsulant profile height, wherein the encapsulant profile height is less than the conductive element profile height,wherein the encapsulant material projects beyond the second surface such that the encapsulant material is substantially colinear with pairs of the conductive elements that are aligned with a central portion of the second perimeter. 22. The method of claim 21, and further comprising disposing conductive elements forming a perimeter on the conductive element pads on the second surface and electrically coupling to at least one of the terminal pads on the second surface via the conductive traces on the second surface, the conductive elements having a conductive element profile height. 23. The method of claim 21, and further comprising providing a die attach pad of dielectric material on the first surface of the substrate and located within the perimeter, the die attach pad for receiving a semiconductor device with bond pads to be placed over the aperture in the substrate, the die attach pad having an opening that aligns with the aperture in the substrate. 24. The method of claim 21, wherein disposing conductive elements further comprises forming solder balls on the conductive element pads. 25. The method of claim 21, and further comprising providing additional conductive element pads on the second surface which are coupled to conductive element pads on the first surface, by forming conductive traces on each surface and coupling the traces to conductive vias through the substrate, wherein at least some of these additional conductive element pads provide an electrically isolated path coupling a conductive element pad on the first surface to a conductive element pad on the second surface that is electrically isolated from any terminal pads on the substrate. 26. The method of claim 21, wherein disposing the die on the first surface of the substrate further comprises forming a die attach pad on the substrate for receiving the semiconductor die having a thickness and mounting a semiconductor die on the die attach, the semiconductor die having a thickness, the combined thicknesses of the semiconductor die and the die attach pad forming a height with respect to the first surface of the substrate that is less than the conductive element profile height.
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