$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Metal line in semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
출원번호 US-0688738 (2010-01-15)
등록번호 US-8120113 (2012-02-21)
우선권정보 KR-10-2006-0096346 (2006-09-29)
발명자 / 주소
  • Choi, Young-Soo
  • Kim, Gyu-Hyun
출원인 / 주소
  • Hynix Semiconductor Inc.
대리인 / 주소
    Kilpatrick Townsend & Stockton LLP
인용정보 피인용 횟수 : 1  인용 특허 : 29

초록

A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion l

대표청구항

1. A metal line in a semiconductor device, the metal line comprising: an insulation layer having trenches formed therein;a barrier metal layer formed over the insulation layer and the trenches;a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches; andan anti-g

이 특허에 인용된 특허 (29)

  1. Cheng-Shien Chen TW; Li-Der Chen TW; Chih-Min Wen TW; Chung Liu TW; Chih-Ching Lin TW, Al-Cu alloy sputtering method with post-metal quench.
  2. Wei-Yung Hsu, Cavity-filling method for reducing surface topography and roughness.
  3. Yu Jick M. (Beaverton OR), Conductor fill reflow with intermetallic compound wetting layer for semiconductor fabrication.
  4. Wetzel Jeffrey Thomas, Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation.
  5. Xu Zheng ; Forster John ; Yao Tse-Yong ; Nulman Jaim ; Chen Fusen, Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer.
  6. Chen, Liang-Yuh; Guo, Ted; Mosley, Roderick Craig; Chen, Fusen, Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug.
  7. Yu, Chen-Hua; Tseng, Horng-Huei; Jang, Syun-Ming; Hu, Chenming, Interconnect with composite barrier layers and method for fabricating the same.
  8. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between circuit metal levels.
  9. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  10. Liu,Chi Wen; Feng,Hsien Ping; Tsao,Jung Chih, Method and apparatus for copper film quality enhancement with two-step deposition.
  11. Chen Kun-Cho,TWX ; Jenq Jason,TWX, Method and structure for preventing bonding pad peel back.
  12. Wang,Ching Ya; Tseng,Joshua; Lo,Henry; Wang,Jean, Method for forming dual damascenes with supercritical fluid treatments.
  13. Kim, Sang Chul; Han, Jae Won, Method for manufacturing semiconductor device.
  14. Gaul Stephen Joseph (Melbourne FL), Method of bonding wafers having vias including conductive material.
  15. Tang, Xianmin; Gopalraja, Praburam; Rengarajan, Suraj; Forster, John C.; Fu, Jianming; Ding, Peijun, Method of depositing a TaN seed layer.
  16. Fujikawa, Takao; Kadoguchi, Makoto; Suzuki, Kohei; Masui, Takuya, Method of forming a wiring film by applying high temperature/high pressure.
  17. Kim, Jea Hee, Method of forming metal line in semiconductor device.
  18. Lawrence D. Wong, Method of forming structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures.
  19. Hwang Soon Hong,KRX, Method of forming wiring in semiconductor device.
  20. Hsu Wei-Yung ; Hong Qi-Zhong ; Havemann Robert H., Method to improve the texture of aluminum metallization.
  21. Wu, Ching-Yuan, Methods of fabricating a stack-gate flash memory array.
  22. Konecni Anthony J. ; Russell Noel, PVD deposition process for CVD aluminum liner processing.
  23. Koyama Kazuhide,JPX, Process for fabricating interconnection of semiconductor device.
  24. Hsu Wei-Yung ; Hong Qi-Zhong, Reduced temperature contact/via filling.
  25. Takayama,Toshio; Narukawa,Kuniyuki; Mizutani,Hiroshi, Semiconductor device having a multilayer interconnection structure and fabrication process thereof.
  26. Lee,Jae Hoon; Nam,Kung Hyon, Semiconductor device wiring and method of manufacturing the same.
  27. McTeer E. Allen, Titanium aluminum alloy wetting layer for improved aluminum filling of damescene trenches.
  28. Tony Chiang ; Peijun Ding ; Barry Chin, Ultra-low resistivity tantalum films and methods for their deposition.
  29. Shih,Jen Chieh; Ho,Bang Ching; Chen,Jian Hong, Via plug formation in dual damascene process.

이 특허를 인용한 특허 (1)

  1. Chen, Erh-Hao; Lin, Cha-Hsin; Ku, Tzu-Kun, Method for manufacturing through substrate via (TSV), structure and control method of TSV capacitance.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로