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Broadcasting collective operation contributions throughout a parallel computer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/76
출원번호 US-0053842 (2008-03-24)
등록번호 US-8122228 (2012-02-21)
발명자 / 주소
  • Faraj, Ahmad
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Biggers & Ohanian LLP
인용정보 피인용 횟수 : 1  인용 특허 : 43

초록

Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for u

대표청구항

1. A method of broadcasting collective operation contributions throughout a parallel computer, the parallel computer comprising a plurality of compute nodes connected together through a data communications network, each compute node having a plurality of processors for use in collective parallel ope

이 특허에 인용된 특허 (43)

  1. Scott Steven L. ; Pribnow Richard D. ; Logghe Peter G. ; Kunkel Daniel L. ; Schwoerer Gerald A., Adaptive congestion control mechanism for modular computer networks.
  2. Hochschild Peter Heiner ; Denneau Monty Montague, Central shared queue based time multiplexed packet switch with deadlock avoidance.
  3. Cotter, David, Communications network.
  4. Pope,Steve L.; Roberts,Derek; Riddoch,David; Yu,Ching; Chiang,John Mingyung; Chu,Der Ren, DMA descriptor queue read and cache write pointer arrangement.
  5. Kato Sadayuki,JPX ; Ishihata Hiroaki,JPX ; Horie Takeshi,JPX ; Inano Satoshi,JPX ; Shimizu Toshiyuki,JPX, Data gathering/scattering system for a plurality of processors in a parallel computer.
  6. Cotter David,GBX ; Tatham Martin C,GBX, Dead reckoning routing of packet data within a network of nodes having generally regular topology.
  7. Ambuel,Jack Robert, Deterministic real time hierarchical distributed computing system.
  8. Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
  9. Michael Olivier, Dynamically matching users for group communications based on a threshold degree of matching of sender and recipient predetermined acceptance criteria.
  10. Blackmore, Robert S.; Jia, Bin; Treumann, Richard R., Facilitating intra-node data transfer in collective communications.
  11. Weis,Bernd X., Fast restoration mechanism and method of determining minimum restoration capacity in a transmission networks.
  12. Cypher Robert E. (Los Gatos CA) Sanz Jorge L. C. (Los Gatos CA), Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressib.
  13. Crosetto Dario B., High-speed, parallel, processor architecture for front-end electronics, based on a single type of ASIC, and method use t.
  14. Passint Randal S. ; Thorson Greg ; Galles Michael B., Hybrid hypercube/torus architecture.
  15. Lovett, Thomas Dean; Mehrotra, Sharad; Nicolaou, Cosmos; Saraiya, Nakul Pratap; Shah, Shreyas B.; White, Myron H.; Jagannathan, Rajesh K.; Shingane, Mangesh, Input/output controller for coupling the processor-memory complex to the fabric in fabric-backplane interprise servers.
  16. Flaig Charles M. (Pasadena CA) Seitz Charles L. (San Luis Rey CA), Inter-computer message routing system with each computer having separate routinng automata for each dimension of the net.
  17. Paul E. McKenney ; Kevin A. Closson ; Raghupathi Malige, Lingering locks with fairness control for multi-node computer systems.
  18. Pechanek,Gerald George; Kurak, Jr.,Charles W., Manifold array processor.
  19. Heller Steven K. (Derry NH), Message transfer system and method for parallel computer with message transfers being scheduled by skew and roll functio.
  20. Carmichael Richard D. ; Ward Joel M. ; Winchell Michael A., Method and apparatus for controlling (N+I) I/O channels with (N) data managers in a homogenous software programmable en.
  21. Hellum, Pål Longva; Kleven, Bjørn Kristian, Method and apparatus for efficient transfer of data packets.
  22. Pechanek Gerald G. ; Pitsianis Nikos P. ; Barry Edwin F. ; Drabenstott Thomas L., Method and apparatus for manifold array processing.
  23. Nilsson Olof E. (Rnninge SEX), Method and apparatus for the connection of a closed ring through a telephone exchange.
  24. Brown, David A., Method and apparatus for wire speed IP multicast forwarding.
  25. Kureya Kimihide,JPX, Method for performing alltoall communication in parallel computers.
  26. Ogasawara Takeshi,JPX ; Komatsu Hideaki,JPX, Method of optimizing recognition of collective data movement in a parallel distributed system.
  27. Stevens Luis F., Method, system and computer program product for managing memory in a non-uniform memory access system.
  28. Frisch Robert Charles, Multicomputer memory access architecture.
  29. Birrittella Mark S. ; Kessler Richard E. ; Oberlin Steven M. ; Passint Randal S. ; Thorson Greg, Multiprocessor computer system with interleaved processing element nodes.
  30. Krishnamoorthy Ashok V. (11188 Caminito Rodar San Diego CA 92126) Kiamilev Fouad (c/o UNC Charlotte ; Dept. of EE ; Smith Hall Room 332 Charlotte NC 28223), Packet-switched self-routing multistage interconnection network having contention-free fanout, low-loss routing, and fan.
  31. Yasuda Yoshiko,JPX ; Tanaka Teruo,JPX, Parallel computer system using properties of messages to route them through an interconnect network and to select virtua.
  32. Maddox James L., Parallel computing system.
  33. Stolfo Salvatore J. (Ridgewood NJ), Parallel processing method.
  34. Hardwick Jonathan C.,GBX, Parallel processing method and system using a lazy parallel data type to reduce inter-processor communication.
  35. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Partitioning of processing elements in a SIMD/MIMD array processor.
  36. Meeker Woodrow L. ; Abercrombie Andrew P., Pattern generation and shift plane operations for a mesh connected computer.
  37. Archer, Charles Jens; Peters, Amanda; Wallenfelt, Brian Paul, Performing process migration with allreduce operations.
  38. Feisullin Farid ; Naylor Bruce ; Raukumar Ajay ; Rogers Lois, Prediction system for RF power distribution.
  39. Nugent Steven F., Routing resource reserve/release protocol for multi-processor computer systems.
  40. Padmanabha I. Venkitakrishnan ; Gopalakrishnan Janakiraman ; Tsen-Gong Jim Hsu ; Rajendra Kumar, Scalable system control unit for distributed shared memory multi-processor systems.
  41. Dunning Dave (Portland OR), Self-timed mesh routing chip with data broadcasting.
  42. Jhanji,Neeraj, Systems for communicating current and future activity information among mobile internet users and methods therefor.
  43. Amemiya, Jiro; Uesugi, Kouki, Video output controller and video card.

이 특허를 인용한 특허 (1)

  1. Naruse, Akira; Kumon, Kouichi, Computer for performing inter-process communication, computer-readable medium storing inter-process communication program, and inter-process communication method.
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