초록 ▼

An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shap

An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.

대표청구항 ▼

1. An interconnect structure comprising: a dielectric material having at least one conductively filled feature located therein;a diffusion barrier separating the at least on conductively filled feature from said dielectric material; andan electromigration (EM) preventing liner located within said at

1. An interconnect structure comprising: a dielectric material having at least one conductively filled feature located therein;a diffusion barrier separating the at least on conductively filled feature from said dielectric material; andan electromigration (EM) preventing liner located within said at least one conductively filled feature that at least partially separates a first conductive region of said at least one conductively filled feature from a second conductive region of said at least one conductively filled feature, wherein said at least one conductively filled feature and said EM preventing liner are confined in an opening that is formed within said dielectric material, said first conductive region and said second conductive region are comprised of a same conductive material, said EM preventing liner is U-shaped and is in direct contact only with an upper portion of a vertical sidewall of the diffusion barrier and wherein no portion of the EM preventing liner is in contact with said dielectric material. 2. An interconnect structure comprising: a dielectric material having at least one conductively filled feature located therein;a diffusion barrier separating the at least on conductively filled feature from said dielectric material; anda horizontal electromigration (EM) preventing liner that separates a lower conductive material from an upper conductive material, wherein said at least one conductively filled feature, said diffusion barrier and said EM preventing liner are confined in an opening that is formed within said dielectric material, said lower conductive material and said upper conductive material are comprised of a same conductive material, and wherein no portion of the horizontal EM preventing liner is in contact with said dielectric material and said horizontal EM preventing liner is vertically offset from a horizontal surface of said diffusion barrier. 3. A method of fabricating an interconnect structure comprising: providing at least one opening in a dielectric material, said at least one opening is lined with a diffusion barrier;forming a first conductive region partially within said at least one opening;forming an electromigration (EM) preventing liner on at least a surface of said first conductive region within said at least one opening, wherein no portion of the EM preventing liner contacts said dielectric material, and said EM preventing liner is selected from the group consisting of an U-shaped EM preventing liner that is in direct contact only with an upper portion of a vertical sidewall of said diffusion barrier, and a horizontal EM liner that has a horizontal surface that is vertically offset from a horizontal surface of the diffusion barrier; andforming a second conductive region on said EM preventing liner filling a remaining portion of said at least one opening, said first and second conductive regions form a conductive feature within said dielectric material, and wherein said first conductive region and said second conductive region are comprised of a same conductive material. 4. The interconnect structure of claim 1 wherein said dielectric material has a dielectric constant of about 4.0 or less. 5. The interconnect structure of claim 1 wherein said EM preventing liner is comprised of Ta, TaN, Ti, TiN, Ru, RuN, RuTaN, RuTaN, Ir, IrCu or a Co alloy including one of W, B, P, Mo and Re. 6. The interconnect structure of claim 1 wherein said at least one conductively filled feature is present in said opening that is formed in said dielectric material, and said one opening is a line opening. 7. The interconnect structure of claim 1 wherein said at least one conductively filled feature is present in said opening that is formed in said dielectric material, and said opening is a combined line and via opening. 8. The interconnect structure of claim 1 wherein said dielectric material is an upper interconnect level that is located atop a lower interconnect level, said lower interconnect level comprising another dielectric material having another conductive feature embedded therein. 9. The interconnect structure of claim 1 wherein said EM preventing liner is selected from the group consisting of Ru, RuN, RuTaN, RuTaN, Ir, IrCu or a Co alloy including one of W, B, P, Mo and Re. 10. The interconnect structure of claim 8 wherein said upper and lower interconnect levels are separated in part by a dielectric capping layer. 11. The interconnect structure of claim 2 wherein said horizontal EM preventing liner is in direct contact with the diffusion barrier. 12. The interconnect structure of claim 2 wherein a space exists between the horizontal EM preventing liner and the diffusion barrier. 13. The interconnect structure of claim 2 wherein said dielectric material has a dielectric constant of about 4.0 or less. 14. The interconnect structure of claim 2 wherein said horizontal EM preventing liner is comprised of Ta, TaN, Ti, TiN, Ru, RuN, RuTaN, RuTaN, Ir, IrCu or a Co alloy including one of W, B, P, Mo and Re. 15. The interconnect structure of claim 2 wherein said at least one conductively filled feature is present in at least one opening that is formed in said dielectric material, and said at least one opening is a line opening. 16. The interconnect structure of claim 2 wherein said at least one conductively filled feature is present in at least one opening that is formed in said dielectric material, and said at least one opening is a combined line and via opening. 17. The interconnect structure of claim 2 wherein said dielectric material is an upper interconnect level that is located atop a lower interconnect level, said lower interconnect level comprising another dielectric material having another conductive feature embedded therein. 18. The interconnect structure of claim 2 wherein said EM preventing liner is selected from the group consisting of Ru, RuN, RuTaN, RuTaN, Ir, IrCu or a Co alloy including one of W, B, P, Mo and Re. 19. The interconnect structure of claim 17 wherein said upper and lower interconnect levels are separated in part by a dielectric capping layer. 20. The method of claim 3 wherein said EM preventing liner is a horizontal EM preventing liner, and said horizontal EM preventing liner is in direct contact with the diffusion barrier. 21. The method of claim 3 wherein said EM preventing liner is a horizontal EM preventing liner, and wherein a space exists between the horizontal EM liner and the diffusion barrier. 22. The method of claim 3 wherein said forming said first conductive region comprises a bottom-up deposition fill process. 23. The method of claim 3 wherein said forming said EM preventing liner comprises a non-selective deposition process. 24. The method of claim 3 wherein said forming said EM preventing liner comprises a directional or selective deposition process. 25. The method of claim 3 further comprising forming a dielectric capping layer on said dielectric material.