Integrated circuits, systems, and methods for reducing leakage currents in a retention mode
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0716363
(2010-03-03)
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등록번호 |
US-8139436
(2012-03-20)
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발명자
/ 주소 |
- Chen, Yen-Huei
- Lee, Cheng Hung
|
출원인 / 주소 |
- Taiwan Semiconductor Manufacturing Company, Ltd.
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대리인 / 주소 |
Lowe Hauptman Ham & Berner, LLP
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인용정보 |
피인용 횟수 :
5 인용 특허 :
4 |
초록
▼
An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A secon
An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.
대표청구항
▼
1. An integrated circuit comprising: at least one memory array for storing data;a first switch coupled with the memory array;a first power line coupled with the first switch, the first power line being capable of providing a first power voltage;a second switch coupled with the memory array;a second
1. An integrated circuit comprising: at least one memory array for storing data;a first switch coupled with the memory array;a first power line coupled with the first switch, the first power line being capable of providing a first power voltage;a second switch coupled with the memory array;a second power line coupled with the second switch, the second power line being capable of supplying a second power voltage for retaining the data during a retention mode; anda third power line coupled with the memory array, the third power line being capable of supplying a third power voltage. 2. The integrated circuit of claim 1 further comprising a voltage provider coupled between the second power line and the third power line, wherein the voltage provider is capable of tracking a change of the third power voltage and providing the second power voltage corresponding to the change of the third power voltage. 3. The integrated circuit of claim 2, wherein the voltage provider comprises: a reference voltage generator having a first output end, the reference voltage generator operable to supply a reference voltage;an amplifier coupled with the first output end of the reference voltage generator, the amplifier having a second output end; anda transistor coupled with the second output end of the amplifier, the transistor being coupled with the second power line, wherein the amplifier and the transistor are configured to modulate the second power voltage being substantially equal to the reference voltage. 4. The integrated circuit of claim 3, wherein the reference voltage generator comprises: at least one transistor being coupled with the third power line; andat least one resistor being coupled with the at least one transistor, wherein the output end of the reference voltage generator is between the at least one transistor and the at least one resistor. 5. The integrated circuit of claim 1, wherein a difference between the second power voltage and the third power voltage is between about 0.5 V and about 0.6 V. 6. The integrated circuit of claim 1, wherein the first power voltage is ground or VSS and the second power voltage is a virtual ground. 7. The integrated circuit of claim 1, wherein each of the first and second switches comprises at least one NMOS transistor. 8. A system comprising: a processor; andan integrated circuit coupled with the processor, the integrated circuit comprising: at least one memory array for storing data;a first switch coupled with the memory array;a first power line coupled with the first switch, the first power line operable to supply a first power voltage;a second switch coupled with the memory array;a second power line coupled with the second switch, the second power line operable to supply a second power voltage for retaining the data during a retention mode; anda third power line coupled with the memory array, the third power line operable to supply a third power voltage. 9. The system of claim 8, wherein the integrated circuit further comprises a voltage provider coupled between the second power line and the third power line and the voltage provider is operable to track a change of the third power voltage and supply the second power voltage corresponding to the change of the third power voltage. 10. The system of claim 9, wherein the voltage provider comprises: a reference voltage generator having a first output end, the reference voltage generator operable to supply a reference voltage;an amplifier coupled with the first output end of the reference voltage generator, the amplifier having a second output end; anda transistor coupled with the second output end of the amplifier, the transistor being coupled with the second power line, wherein the amplifier and the transistor are configured to modulate the second power voltage being substantially equal to the reference voltage. 11. The system of claim 10, wherein the reference voltage generator comprises: at least one transistor being coupled with the third power line; andat least one resistor being coupled with the at least one transistor, wherein the output end of the reference voltage generator is between the at least one transistor and the at least one resistor. 12. The system of claim 8, wherein a difference between the second power voltage and the third power voltage is between about 0.5 V and about 0.6 V. 13. The system of claim 8, wherein the first power voltage is ground or VSS and the second power voltage is a virtual ground. 14. The system of claim 8, wherein each of the first and second switches comprises at least one NMOS transistor. 15. A method for reducing a leakage current of a memory array at a retention mode, the method comprising: coupling the memory array with a first power line providing a first power voltage, if the memory array operates at an active mode; andcoupling the memory array with a second power line providing a second power voltage, if the memory array operates at a retention mode. 16. The method of claim 15 further comprising: coupling the memory array with a third power line being capable of providing a third power voltage; andtracking a change of the third power voltage to provide the second power voltage corresponding to the change of the third power voltage. 17. The method claim 15, wherein a difference between the second power voltage and the third power voltage is between about 0.5 V and about 0.6 V. 18. The method of claim 15, wherein the first power voltage is ground or VSS and the second power voltage is a virtual ground. 19. The method of claim 15, wherein coupling the memory array with the first power line comprises: turning on a first switch to couple the memory array with the first power line. 20. The method of claim 15, wherein coupling the memory array with the second power line comprises: turning on a second switch to couple the memory array with the second power line.
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Kolla, Yeshwant Nagaraj; Natekar, Neel Shashank, Selective coupling of power rails to a memory domain(s) in a processor-based system.
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