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Executing a gather operation on a parallel computer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
  • G06F-015/76
  • G06F-011/00
출원번호 US-0754740 (2007-05-29)
등록번호 US-8140826 (2012-03-20)
발명자 / 주소
  • Archer, Charles J.
  • Ratterman, Joseph D.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Biggers & Ohanian, LLP
인용정보 피인용 횟수 : 1  인용 특허 : 44

초록

Methods, apparatus, and computer program products are disclosed for executing a gather operation on a parallel computer according to embodiments of the present invention. Embodiments include configuring, by the logical root, a result buffer or the logical root, the result buffer having positions, ea

대표청구항

1. A method for executing a gather operation on a parallel computer, the parallel computer comprising a plurality of compute nodes, the compute nodes organized into at least one operational group of compute nodes for collective parallel operations of the parallel computer, each compute node in the o

이 특허에 인용된 특허 (44)

  1. Scott Steven L. ; Pribnow Richard D. ; Logghe Peter G. ; Kunkel Daniel L. ; Schwoerer Gerald A., Adaptive congestion control mechanism for modular computer networks.
  2. Bhanot, Gyan; Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Steinmacher Burow, Burkhard D.; Takken, Todd E.; Vranas, Pavlos M., Class network routing.
  3. Cotter, David, Communications network.
  4. Pope,Steve L.; Roberts,Derek; Riddoch,David; Yu,Ching; Chiang,John Mingyung; Chu,Der Ren, DMA descriptor queue read and cache write pointer arrangement.
  5. Kato Sadayuki,JPX ; Ishihata Hiroaki,JPX ; Horie Takeshi,JPX ; Inano Satoshi,JPX ; Shimizu Toshiyuki,JPX, Data gathering/scattering system for a plurality of processors in a parallel computer.
  6. Yosimoto, Atuyuki; Hayasaka, Kazumi; Saito, Hiroshi; Suetsugu, Yoshimasa, Data transfer apparatus and method.
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  8. Ambuel,Jack Robert, Deterministic real time hierarchical distributed computing system.
  9. Connor, Patrick L.; McVay, Robert G., Direct memory access transfer reduction method and apparatus to overlay data on to scatter gather descriptors for bus-mastering I/O controllers.
  10. Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
  11. Michael Olivier, Dynamically matching users for group communications based on a threshold degree of matching of sender and recipient predetermined acceptance criteria.
  12. Archer, Charles J.; Ratterman, Joseph D., Executing scatter operation to parallel computer nodes by repeatedly broadcasting content of send buffer partition corresponding to each node upon bitwise OR operation.
  13. Blackmore, Robert S.; Jia, Bin; Treumann, Richard R., Facilitating intra-node data transfer in collective communications.
  14. Weis,Bernd X., Fast restoration mechanism and method of determining minimum restoration capacity in a transmission networks.
  15. Shin Kang G. (Ann Arbor MI) Chen Ming-Syan (Yorktown Heights NY) Kandlur Dilip D. (Ann Arbor MI), Hexagonal mesh multiprocessor system.
  16. Cypher Robert E. (Los Gatos CA) Sanz Jorge L. C. (Los Gatos CA), Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressib.
  17. Crosetto Dario B., High-speed, parallel, processor architecture for front-end electronics, based on a single type of ASIC, and method use t.
  18. Lovett, Thomas Dean; Mehrotra, Sharad; Nicolaou, Cosmos; Saraiya, Nakul Pratap; Shah, Shreyas B.; White, Myron H.; Jagannathan, Rajesh K.; Shingane, Mangesh, Input/output controller for coupling the processor-memory complex to the fabric in fabric-backplane interprise servers.
  19. Flaig Charles M. (Pasadena CA) Seitz Charles L. (San Luis Rey CA), Inter-computer message routing system with each computer having separate routinng automata for each dimension of the net.
  20. Heller Steven K. (Derry NH), Message transfer system and method for parallel computer with message transfers being scheduled by skew and roll functio.
  21. Carmichael Richard D. ; Ward Joel M. ; Winchell Michael A., Method and apparatus for controlling (N+I) I/O channels with (N) data managers in a homogenous software programmable en.
  22. Hellum, Pål Longva; Kleven, Bjørn Kristian, Method and apparatus for efficient transfer of data packets.
  23. Nilsson Olof E. (Rnninge SEX), Method and apparatus for the connection of a closed ring through a telephone exchange.
  24. Brown, David A., Method and apparatus for wire speed IP multicast forwarding.
  25. Kureya Kimihide,JPX, Method for performing alltoall communication in parallel computers.
  26. Ogasawara Takeshi,JPX ; Komatsu Hideaki,JPX, Method of optimizing recognition of collective data movement in a parallel distributed system.
  27. Stevens Luis F., Method, system and computer program product for managing memory in a non-uniform memory access system.
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  30. Yasuda Yoshiko,JPX ; Tanaka Teruo,JPX, Parallel computer system using properties of messages to route them through an interconnect network and to select virtua.
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  32. Stolfo Salvatore J. (Ridgewood NJ), Parallel processing method.
  33. Hardwick Jonathan C.,GBX, Parallel processing method and system using a lazy parallel data type to reduce inter-processor communication.
  34. Nakagoshi Junji (Tokyo JPX) Hamanaka Naoki (Tokyo JPX) Chiba Hiroyuki (Koyasu JPX) Higuchi Tatsuo (Fuchu JPX) Shutoh Shinichi (Kokubunji JPX) Ogata Yasuhiro (Akishima JPX) Takeuchi Shigeo (Hannou JPX, Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks an.
  35. Higuchi Tatsuo,JPX ; Isobe Tadaaki,JPX ; Nakagoshi Junji,JPX ; Takeuchi Shigeo,JPX ; Toba Tatsuru,JPX ; Yasuda Yoshiko,JPX ; Tanaka Teruo,JPX ; Nakagawa Takayuki,JPX ; Saeki Yuji,JPX, Parallel processor system with a broadcast message serializing circuit provided within a network.
  36. Ogata Yasuhiro,JPX ; Nakagoshi Junji,JPX ; Hamanaka Naoki,JPX ; Chiba Hiroyuki,JPX ; Shutoh Shinichi,JPX ; Higuchi Tatsuo,JPX ; Takeuchi Shigeo,JPX ; Toba Taturu,JPX ; Tanaka Teruo,JPX, Partial broadcast method in parallel computer and a parallel computer suitable therefor.
  37. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Partitioning of processing elements in a SIMD/MIMD array processor.
  38. Meeker Woodrow L. ; Abercrombie Andrew P., Pattern generation and shift plane operations for a mesh connected computer.
  39. Archer, Charles Jens; Peters, Amanda; Wallenfelt, Brian Paul, Performing process migration with allreduce operations.
  40. Feisullin Farid ; Naylor Bruce ; Raukumar Ajay ; Rogers Lois, Prediction system for RF power distribution.
  41. Nugent Steven F., Routing resource reserve/release protocol for multi-processor computer systems.
  42. Dunning Dave (Portland OR), Self-timed mesh routing chip with data broadcasting.
  43. Jhanji,Neeraj, Systems for communicating current and future activity information among mobile internet users and methods therefor.
  44. Amemiya, Jiro; Uesugi, Kouki, Video output controller and video card.

이 특허를 인용한 특허 (1)

  1. Hinds, Christopher Neal; Lutz, David Raymond, Arithmetic operation input-output equality detection.
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