IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0007822
(2011-01-17)
|
등록번호 |
US-8143150
(2012-03-27)
|
우선권정보 |
KR-10-2010-0016267 (2010-02-23) |
발명자
/ 주소 |
|
출원인 / 주소 |
- Samsung Electronics Co., Ltd.
|
대리인 / 주소 |
F. Chau & Associates, LLC
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
1 |
초록
▼
A method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the well impurity region, the upper impur
A method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region. The semiconductor substrate is etched to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns. An isolation layer filling the first and second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively is formed.
대표청구항
▼
1. A method of fabricating a semiconductor device, comprising: forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate, wherein the lower impurity region has a different conductivity type from a conductivity type of the well impurity region,
1. A method of fabricating a semiconductor device, comprising: forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate, wherein the lower impurity region has a different conductivity type from a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region;etching the semiconductor substrate to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns, wherein the upper semiconductor patterns have sidewalls vertically arranged with facing sidewalls of the lower semiconductor patterns and facing each other, a first space between the upper semiconductor patterns projecting from the lower semiconductor patterns, and a second space between the lower semiconductor patterns having a bottom surface disposed at a lower level than the lower impurity region, and wherein top surfaces of the lower semiconductor patterns disposed between the upper semiconductor patterns are disposed at a lower level than the upper impurity region and disposed at a higher level than a bottom surface of the lower impurity region; andforming an isolation layer filling the first and the second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively. 2. The method of claim 1, wherein the lower impurity region includes a first impurity region and a second impurity region disposed on the first impurity region, the first impurity region and the second impurity region having the same conductivity type as one another and the first impurity region having a higher impurity concentration than an impurity concentration of the second impurity region, and the lower impurity region and the upper impurity region constitute a diode. 3. The method of claim 1, wherein the forming of the lower and upper semiconductor patterns comprises: forming hard masks on the semiconductor substrate having the impurity regions, the hard masks being formed in the shape of lines of a first orientation;etching the semiconductor substrate using the hard masks as etch masks to form preliminary trenches;forming a sacrificial layer filling the preliminary trenches;forming sacrificial masks on the substrate having the sacrificial layer, the sacrificial masks being formed in the shape of lines of a second orientation crossing the first orientation;etching the hard masks using the sacrificial masks as etch masks to form hard mask patterns;removing the sacrificial masks and the sacrificial layer; andetching bottom regions of the preliminary trenches formed in the semiconductor substrate and the semiconductor substrate between the preliminary trenches using the hard mask patterns as etch masks to form the lower semiconductor patterns spaced apart from each other and the upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns. 4. The method of claim 1, wherein the forming of the lower semiconductor patterns and the upper semiconductor patterns comprise: forming hard masks on the semiconductor substrate having the impurity regions, the hard masks being formed in the shape of lines of a first orientation;etching the semiconductor substrate using the hard masks as etch masks to form trenches, the trenches having bottom regions disposed at a lower level than the lower impurity region;forming a sacrificial layer filling the trenches;forming sacrificial masks on the semiconductor substrate having the sacrificial layer, the sacrificial masks being formed in the shape of lines of a second orientation crossing the first orientation;etching the hard masks using the sacrificial masks as etch masks to form a plurality of hard mask patterns spaced apart from each other;etching the semiconductor substrate between the trenches to a depth at a level lower than the upper impurity region and at a level higher than a bottom surface of the lower impurity region using the hard mask patterns and the sacrificial layer as etch masks to form the lower semiconductor patterns and the upper semiconductor patterns that are defined between the trenches; andremoving the sacrificial masks and the sacrificial layer. 5. The method of claim 1, further comprising: partially etching the isolation layer to form a preliminary lower isolation pattern filling a space between the lower semiconductor patterns and exposing sidewalls of the upper semiconductor patterns where the upper impurity region is disposed;forming sidewall spacers surrounding the exposed sidewalls of the upper semiconductor patterns, the sidewall spacers being spaced apart from each other;partially etching the preliminary lower isolation pattern to form the lower isolation pattern, a top surface of the lower isolation pattern being disposed at a higher level than a bottom surface of the lower impurity region;forming a metal-semiconductor compound layer on sidewalls of the lower semiconductor patterns, which are not covered with the lower isolation pattern, and on top surfaces of the lower semiconductor patterns between the upper semiconductor patterns;forming an insulating material layer on the semiconductor substrate having the metal-semiconductor compound layer; andplanarizing the insulating material layer until the hard mask patterns are exposed to form an upper isolation layer. 6. The method of claim 5, wherein the metal-semiconductor compound layer extends to partially cover sidewalls of the upper semiconductor patterns, is disposed at a lower level than the upper impurity region, and is spaced apart from the upper impurity region. 7. A method of fabricating a semiconductor device, comprising: forming a lower impurity region and an upper impurity region having different conductivity types than one another in a semiconductor substrate, the upper impurity region being disposed over the lower impurity region;etching the semiconductor substrate to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns, and a space between the lower semiconductor patterns having a bottom surface disposed at a lower level than the lower impurity region, and wherein top surfaces of the lower semiconductor patterns disposed between the upper semiconductor patterns are disposed at a lower level than the upper impurity region and disposed at a higher level than the bottom surface of the lower impurity region;forming spacers covering sidewalls of the upper semiconductor patterns to surround a boundary region between the lower impurity region and the upper impurity region;forming a lower isolation pattern partially filling the space between the lower semiconductor patterns, wherein a top surface of the lower isolation pattern being disposed at a higher level than the bottom surface of the lower impurity region; andforming a metal-semiconductor compound layer on sidewalls of the lower semiconductor patterns, which are not covered with the lower isolation pattern, and on top surfaces of the lower semiconductor patterns between the upper semiconductor patterns. 8. The method of claim 7, wherein the metal-semiconductor compound layer extends to partially cover sidewalls of the upper semiconductor patterns, is disposed at a lower level than the upper impurity region, and is spaced apart from the upper impurity region. 9. The method of claim 7, wherein the lower impurity region includes a first impurity region and a second impurity region disposed on the first impurity region, the first impurity region and the second impurity region having the same conductivity type as one another, and the first impurity region having a higher impurity concentration than an impurity concentration of the second impurity region. 10. The method of claim 7, further comprising forming a well impurity region having a same conductivity type as the upper impurity region and having a lower impurity concentration than the upper impurity region in the semiconductor substrate below the lower impurity region, wherein the well impurity region is formed in the semiconductor substrate between the lower semiconductor patterns, extends into the lower semiconductor patterns and is disposed at a lower level than the lower impurity region. 11. The method of claim 7, wherein the spacers surround sidewalls of the upper semiconductor patterns where the upper impurity region is disposed, and extend towards sidewalls of the upper semiconductor patterns where the lower impurity region is disposed. 12. The method of claim 7, wherein the forming of the spacers comprises: forming a preliminary isolation layer on the semiconductor substrate having the lower and upper semiconductor patterns;partially etching the preliminary isolation layer to form a preliminary isolation pattern, the preliminary isolation pattern filling the spaces between the lower semiconductor patterns, covering top surfaces of the lower semiconductor patterns disposed between the upper semiconductor patterns, and a top surface of the preliminary isolation pattern being disposed at a lower level than the upper impurity region; andforming the spacers covering sidewalls of the upper semiconductor patterns, which are not covered with the preliminary isolation pattern. 13. The method of claim 12, wherein the forming of the lower isolation pattern comprises: partially etching the preliminary isolation pattern, exposing top surfaces of the lower semiconductor patterns disposed between the upper semiconductor patterns, and exposing sidewalls of the lower semiconductor patterns where the lower impurity region remains. 14. The method of claim 7, wherein the forming of the lower semiconductor patterns and the upper semiconductor patterns comprises: forming hard masks on the semiconductor substrate, the hard masks being formed in the shape of lines parallel to each other and having a first orientation;etching the semiconductor substrate using the hard masks as etch masks to form preliminary trenches;forming a sacrificial layer filling the preliminary trenches;forming sacrificial masks on the substrate having the sacrificial layer, the sacrificial masks being formed in the shape of lines of a second orientation crossing the first orientation;etching the hard masks using the sacrificial masks as etch masks to form a plurality of hard mask patterns spaced apart from each other;removing the sacrificial masks and the sacrificial layer; andetching bottom regions of the preliminary trenches formed in the semiconductor substrate and the semiconductor substrate between the preliminary trenches using the hard mask patterns as etch masks. 15. The method of claim 7, wherein the forming of the lower semiconductor patterns and the upper semiconductor patterns comprises: forming hard masks on the semiconductor substrate, the hard masks being formed in the shape of lines parallel to each other and having a first orientation;etching the semiconductor substrate using the hard masks as etch masks and forming trenches, the trenches having bottom regions disposed at a lower level than the lower impurity region;forming a sacrificial layer filling the trenches;forming sacrificial masks on the semiconductor substrate having the sacrificial layer, the sacrificial masks being formed in the shape of lines of a second orientation crossing the first orientation;etching the hard masks using the sacrificial masks as etch masks to form a plurality of hard mask patterns spaced apart from each other;etching the semiconductor substrate between the trenches to a depth at a level lower than the upper impurity region and at a level higher than a bottom surface of the lower impurity region using the hard mask patterns and the sacrificial layer as etch masks to form the lower semiconductor patterns and the upper semiconductor patterns that are defined between the trenches; andremoving the sacrificial masks and the sacrificial layer. 16. The method of claim 7, further comprising: forming an insulating material layer on the semiconductor substrate having the metal-semiconductor compound layer;planarizing the insulating material layer; andforming an upper isolation layer,wherein the upper isolation layer is formed on the lower isolation pattern, and fills between the lower semiconductor patterns that are not filled with the lower isolation pattern and between the upper semiconductor patterns. 17. The method of claim 7, further comprising: forming conductive patterns electrically connected to the upper impurity regions;forming information storage elements on the conductive patterns; andforming conductive lines in the shape of lines having an orientation crossing the lower semiconductor patterns on the information storage elements. 18. The method of claim 7, wherein the spacers are formed of a different material from the lower isolation pattern. 19. The method of claim 7, further comprising removing the spacers after forming the metal-semiconductor compound layer. 20. A method of fabricating a semiconductor device, comprising: performing an ion-implantation process to form a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate, wherein the lower impurity region has a different conductivity type from a conductivity type of the well impurity region, the upper impurity region has a different conductivity type from than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region, wherein the upper impurity region and the lower impurity region constitute a diode and wherein a lower part of the lower impurity region constitutes word lines;etching the semiconductor substrate to form lower semiconductor patterns, upper semiconductor patterns upwardly projecting from predetermined regions of the lower semiconductor patterns, a first space between the upper semiconductor patterns projecting from the lower semiconductor patterns, and a second space between the lower semiconductor patterns having a bottom surface disposed at a lower level than the lower impurity region, and wherein top surfaces of the lower semiconductor patterns disposed between the upper semiconductor patterns are disposed at a lower level than the upper impurity region and disposed at a higher level than a bottom surface of the lower impurity region;forming an isolation layer filling the first and the second spaces between the lower semiconductor patterns and between the upper semiconductor patterns, respectively;forming a first interlayer insulating layer on the semiconductor substrate having the isolation layer;forming holes penetrating the first interlayer insulating layer exposing the upper impurity regions;performing a silicide process to form a metal-semiconductor compound layer on the upper impurity regions;forming metal plugs on the metal-semiconductor compound layer by filling the holes in the first interlayer insulating layer;foaming a second interlayer insulating layer on the semiconductor substrate having the metal plugs;forming first conductive patterns penetrating the second interlayer insulating layer and electrically connected to the metal plugs;sequentially forming information storage patterns and second conductive patterns on the semiconductor substrate having the first conductive patterns, wherein the information storage elements include a phase-change material layer whose resistance to a flowing current varies depending on a phase, wherein the information storage patterns are electrically connected to the diode formed of the upper impurity region and the lower impurity region through the first conductive patterns, the metal plugs and the metal semiconductor compound layer; andforming conductive lines on the second conductive patterns in the shape of lines crossing the lower semiconductor patterns and wherein the conductive lines constitute bit lines.
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