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Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0258100 (2008-10-24) |
등록번호 | US-8145881 (2012-03-27) |
우선권정보 | DE-101 10 530 (2001-03-05); DE-030 19 428 (2003-08-28); EP-03019428 (2003-08-28); EP-03025911 (2003-11-05); DE-103 57 284 (2003-12-05); EP-03028953 (2003-12-17); EP-03079015 (2003-12-17); EP-04002604 (2004-02-05); EP-04002719 (2004-02-06); EP-04003258 (2004-02-13); EP-04004885 (2004-03-02); EP-04075654 (2004-03-02); EP-04005403 (2004-03-08); EP-04013557 (2004-06-09); EP-04018267 (2004-08-02); EP-04077206 (2004-08-02) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 1 인용 특허 : 542 |
A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the f
A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.
1. A data processing device comprising: a multidimensional array of data processing coarse grained logic elements (PAEs) that are operated at a first clock rate and that communicate with at least one of (a) one another and (b) other elements via at least one of (i) busses and (ii) communication line
1. A data processing device comprising: a multidimensional array of data processing coarse grained logic elements (PAEs) that are operated at a first clock rate and that communicate with at least one of (a) one another and (b) other elements via at least one of (i) busses and (ii) communication lines operated at a second clock rate;wherein: the first clock rate is higher than the second;the coarse grained logic elements comprise storage means for storing data needed to be processed;the array is controlled to perform data-flow data processing;the data-flow data processing has a main data flow direction;said coarse grained logic elements include at least one coarse grained hardware logic element adapted to effect data processing while allowing data to flow in said main data flow direction;the at least one coarse grained logic element includes a coarse grained logic element that includes a first ALU having an upstream input side and a data downstream output side and a second ALU that provides for data flow in a direction reverse from that of the first ALU; andan instruction set for the first ALU is a subset of an instruction set for the second ALU.
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