Methods and systems for power management in a data processing system
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-001/32
G06F-001/03
출원번호
US-0040003
(2011-03-03)
등록번호
US-8145928
(2012-03-27)
발명자
/ 주소
de Cesare, Joshua
Semeria, Bernard
Smith, Michael
출원인 / 주소
Apple Inc.
대리인 / 주소
Blakely, Sokoloff, Taylor & Zafman LLP
인용정보
피인용 횟수 :
9인용 특허 :
24
초록▼
Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general
Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.
대표청구항▼
1. A data processing system on a monolithic semiconductor substrate which provides a system on a chip (SOC), the data processing system comprising: a general purpose processing unit;a graphics processing unit;at least one peripheral interface controller;at least one bus coupled to the general purpos
1. A data processing system on a monolithic semiconductor substrate which provides a system on a chip (SOC), the data processing system comprising: a general purpose processing unit;a graphics processing unit;at least one peripheral interface controller;at least one bus coupled to the general purpose processing unit, the graphics processing unit, and the at least one peripheral interface controller;a power controller coupled to at least the general purpose processing unit and the graphics processing unit, the power controller being configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit, and the power controller being configured to turn power off for the graphics processing unit in response to a second state of an instruction queue of the graphics processing unit, wherein the first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions and wherein the graphics processing unit has its power turned off while an image, generated by the graphics processing unit, is being displayed by the data processing system, and wherein a software driver of the graphics processing unit provides, in response to the second state, a message, representing the second state, to the general purpose processing unit and the general purpose processing unit, in response to the message, causes the power controller to turn power off for the graphics processing unit, and wherein power for the graphics processing unit is turned off without using a timer to time a duration of non-use of the graphics processing unit. 2. The data processing system of claim 1 wherein, over a period of time, the power for the general purpose processing unit is turned off after a first period of time and the power for the graphics processing unit (GPU) is turned on such that it is on for a second period of time after the first period of time and then power to the general purpose processing unit is turned on to allow the general purpose processing unit to turn off power for the GPU after the second period of time. 3. The data processing system of claim 2 wherein the short period of time is less than 60 seconds. 4. The data processing system of claim 1 wherein the general purpose processing unit (GPU) receives a maximum voltage, while operating at maximum frequency, when power is on for the GPU and receives about zero voltage when power is off for the GPU, and wherein the graphics processing unit (GPU) receives its maximum voltage, while operating its maximum frequency, when power is on for the GPU and receives about zero voltage when power is off for the GPU. 5. The data processing system of claim 1 wherein the at least one peripheral interface controller is at least one of (a) a data codec; (b) a camera interface controller; (c) a wireless interface controller; (d) a controller for a dock; (e) a serial bus interface controller; (f) a digital signal processor; and (g) a display controller, and wherein the data processing system further comprises: a power management unit which is external to the SOC and is coupled to the power controller on the SOC and is coupled to the general purpose processing unit. 6. A machine implemented method comprising: determining a state of an instruction queue of a graphics processing unit;turning off power to the graphics processing unit in response to determining that the instruction queue of the graphics processing unit (GPU) has either no instructions or instructions for only future events or actions, wherein the GPU has its power turned off while an image, generated by the graphics processing unit, is being displayed;determining a state of an instruction queue of a general purpose processing unit;turning off power to the general purpose processing unit in response to determining that the instruction queue of the general purpose processing unit has either no instructions or instructions for only future events or actions, wherein a software driver of the GPU sends, in response to determining that the instruction queue has either no instructions or instructions for only future events or actions, a message to the general purpose processing unit indicating the state of the instruction queue of the GPU, and the general purpose processing unit causes a power controller to turn power off for the GPU and wherein power for the GPU is turned off without using a timer to time a duration of non-use of the GPU. 7. The method of claim 6 wherein the general purpose processing unit creates instructions for the GPU while the GPU's power is off and then causes, after the instructions for the GPU have been created, power to be turned on for the GPU which processes the instructions for the GPU and then, after the GPU completes processing of the instructions for the GPU, the power to the GPU is turned off if the instruction queue of the GPU has either no instructions or instructions for only future events or actions. 8. A machine readable non-transitory storage medium containing executable program instructions which cause a data processing system to perform a method comprising: determining a state of an instruction queue of a graphics processing unit;turning off power to the graphics processing unit in response to determining that the instruction queue of the graphics processing unit (GPU) has either no instructions or instructions for only future events or actions, wherein the GPU has its power turned off while an image, generated by the graphics processing unit, is being displayed;determining a state of an instruction queue of a general purpose processing unit;turning off power to the general purpose processing unit in response to determining that the instruction queue of the general purpose processing unit has either no instructions or instructions for only future events or actions, wherein a software driver of the GPU sends, in response to determining that the instruction queue has either no instructions or instructions for only future events or actions, a message to the general purpose processing unit indicating the state of the instruction queue of the GPU, and the general purpose processing unit causes a power controller to turn power off for the GPU and wherein power for the GPU is turned off without using a timer to time a duration of non-use of the GPU. 9. The non-transitory storage medium of claim 8 wherein the general purpose processing unit creates instructions for the GPU while the GPU's power is off and then causes, after the instructions for the GPU have been created, power to be turned on for the GPU which processes the instructions for the GPU and then, after the GPU completes processing of the instructions for the GPU, the power to the GPU is turned off if the instruction queue of the GPU has either no instructions or instructions for only future events or actions.
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이 특허에 인용된 특허 (24)
Kommrusch,Steven J.; Landguth,Mark A., Apparatus and method for initiating a sleep state in a system on a chip device.
Datar, Rajendra; Ghanekar, Sachin; Gogte, Ravindra; Gracias, Sebastian, Dynamically activating and deactivating selected circuit blocks of a data processing integrated circuit during execution of instructions according to power code bits appended to selected instructions.
Alvar Antonio Dean ; Patrick Edward Perry ; Sebastian Theodore Ventrone, Managing VT for reduced power using power setting commands in the instruction stream.
Tobias,David F.; Menezes,Evandro; Russell,Richard; Altmejd,Morrie, System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit.
Kardach,James P., System for selectively generating real-time interrupts and selectively processing associated data when it has higher priority than currently executing non-real-time operation.
Louis B. Hobson, System with control registers for managing computer legacy peripheral devices using an advanced configuration power interface software power management system.
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