IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
|
출원번호 |
US-0843271
(2007-08-22)
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등록번호 |
US-8151042
(2012-04-03)
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발명자
/ 주소 |
- Coteus, Paul W.
- Gower, Kevin C.
- Maule, Warren E.
- Tremaine, Robert B.
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출원인 / 주소 |
- International Business Machines Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
241 |
초록
▼
A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets
A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets including upstream identification tags. The memory controller also includes a mechanism having instructions for facilitating determining if a received data packet is in response to a request from the memory controller. Input to the determining includes an upstream identification tag included in the received data packet. If the received data packet is determined to be in response to a request from the memory controller, then the received data packet is matched to the request, thereby allowing the memory controller to operate with indeterminate data response times.
대표청구항
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1. A memory controller in a memory system, the memory controller comprising: a first mechanism for receiving data packets at indeterminate times via an upstream channel, the first mechanism comprising a means for identifying bits received via the upstream channel as corresponding to a received data
1. A memory controller in a memory system, the memory controller comprising: a first mechanism for receiving data packets at indeterminate times via an upstream channel, the first mechanism comprising a means for identifying bits received via the upstream channel as corresponding to a received data packet; anda second mechanism including instructions for facilitating: determining if the received data packet is in response to a request from the memory controller, wherein input to the determining includes an upstream identification tag included in the received data packet, the upstream identification tag comprising at least one bit indicating that the received data packet is in response to a request from the memory controller or indicating that the received data packet is not in response to a request from the memory controller;determining if the received data packet is a partial response and that additional data related to the received data packet will be transferred in subsequent data packets, the determining responsive to inspecting a continuation bit in the received data packet; andmatching the received data packet to the request responsive to determining that the received data packet is in response to a request from the memory controller. 2. The memory controller of claim 1, wherein the second mechanism further includes instructions for facilitating: if the received data packet is determined not to be in response to a request from the memory controller, then processing the received data packet in response to contents of the upstream identification tag. 3. The memory controller of claim 2 wherein the upstream identification tag further comprises a physical address range of the data and a source of the data. 4. The memory controller of claim 3 wherein the upstream identification tag further includes one or more of a reason for the unrequested data, a priority of the data, one or more continuation bits and fault tolerant encoding. 5. The memory controller of claim 2 wherein the processing includes storing at least a subset of the received data packet in a cache accessible by the memory controller. 6. The memory controller of claim 1 wherein the upstream identification tag further includes a source of the request, a priority of the request, and a request identifier. 7. The memory controller of claim 1 wherein the upstream identification tag further includes one or more of a source of the data, fault tolerant encoding, and one or more continuation bits. 8. The memory controller of claim 1 wherein the request includes a downstream identification tag. 9. The memory controller of claim 8 wherein contents of the downstream identification tag are included in the upstream identification tag of a data packet that is received via an upstream channel in response to the request. 10. The memory controller of claim 8 wherein the downstream identification tag includes a priority of the request, a request identifier, and identifies the memory controller as the source of the request. 11. The memory controller of claim 1, wherein the identifying of the bits received via the upstream channel as corresponding to a received data packet comprises identifying at least one frame start indicator bit received via the upstream channel. 12. The memory controller of claim 1, wherein the bits received on the upstream channel are received during a plurality of bus cycles and the bits corresponding to the data packet are received during any of the plurality of bus cycles. 13. A method for providing indeterminate data response times in a memory system, the method comprising: monitoring an upstream channel in a memory system;determining that bits received on the upstream channel correspond to a data packet, the determining responsive to at least one bit received on the upstream channel at an indeterminate time indicating that the received bits correspond to the data packet;receiving the data packet at an upstream device via the upstream channel, the data packet including an upstream identification tag and data, the upstream identification tag comprising at least one bit indicating that the data packet is in response to a request from the upstream device or indicating that the data packet is not in response to a request from the upstream device;determining if the data packet is a partial response and that additional data related to the data packet will be transferred in subsequent data packets, the determining responsive to inspecting a continuation bit in the data packet;determining if the received data packet is in response to a request from the upstream device, wherein input to the determining includes the upstream identification tag;matching the received data packet to the request responsive to determining that the received data packet is in response to a request from the upstream device; andprocessing the data packet according to bits included in the received data packet, responsive to determining that the received data packet is not in response to a request from the upstream device. 14. The method of claim 13 wherein if the data packet is determined not to be in response to a request from the upstream device, then the upstream identification tag further comprises a physical address range of the data, and a source of the data. 15. The method of claim 14 wherein the upstream identification tag further includes one or more of a reason for the unrequested data, a priority of the data, one or more continuation bits and fault tolerant encoding. 16. The method of claim 13 wherein the matching includes matching a request identifier in a downstream identification tag associated with the request to a request identifier in the upstream identification tag. 17. The method of claim 13 wherein the upstream device is a memory controller. 18. The method of claim 13, wherein the at least one bit on the upstream channel indicating that the received bits correspond to the data packet is at least one frame start indicator bit. 19. The method of claim 13, wherein the data packet is received at an indeterminate time relative to a selected bus cycle of the upstream channel. 20. A hub device in a memory system, the hub device comprising: a mechanism for creating a local data packet, the local data packet including an upstream identification tag for identifying contents of the data packet;a mechanism for transmitting the local data packet to an upstream device, the upstream device one of a memory controller and an other hub device; a mechanism for receiving data packets at indeterminate times via an upstream channel, the mechanism comprising a means for identifying bits received via the upstream channel as corresponding to a received data packet;a mechanism for storing a plurality of received data packets and forwarding each of the plurality of received data packets according to a priority and a chronological order, the priority determined by a priority field within each of the plurality of received data packets, and the chronological order determined by an order of a command requesting the received data packets; anda mechanism including instructions for facilitating:determining if the received data packet is in response to a request from the hub device, wherein input to the determining includes an upstream identification tag included in the received data packet the upstream identification tag comprising at least one bit indicating that the received data packet is in response to a request from the hub device or indicating that the received data packet is not in response to a request from the hub device; andmatching the received data packet to the request responsive to determining that the received data packet is in response to a request from the hub device.
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