IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0188613
(2011-07-22)
|
등록번호 |
US-8159054
(2012-04-17)
|
우선권정보 |
JP-2004-106224 (2004-03-31) |
발명자
/ 주소 |
- Satou, Yukihiro
- Uno, Tomoaki
- Matsuura, Nobuyoshi
- Shiraishi, Masaki
|
출원인 / 주소 |
- Renesas Electronics Corporation
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
0 인용 특허 :
9 |
초록
▼
The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOSωFET for a high side switch and a power MOSωFET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power
The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOSωFET for a high side switch and a power MOSωFET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
대표청구항
▼
1. A semiconductor device including a DC-DC converter, comprising: a first chip mounting portion having a first lead for use as an input for the DC-DC converter;a second chip mounting portion having a second lead for use as an output for the DC-DC converter;a third chip mounting portion having a thi
1. A semiconductor device including a DC-DC converter, comprising: a first chip mounting portion having a first lead for use as an input for the DC-DC converter;a second chip mounting portion having a second lead for use as an output for the DC-DC converter;a third chip mounting portion having a third lead;a fourth lead to supply a ground potential to the DC-DC converter;a first semiconductor chip including a high side MOSFET of the DC-DC converter, the first semiconductor chip being mounted over the first chip mounting portion, the first semiconductor chip having an obverse surface, a reverse surface opposite the obverse surface, a first side, and a second side intersecting the first side,the first semiconductor chip having a first gate electrode pad and a first source electrode pad on the obverse surface, and a first drain electrode on the reverse surface,the first drain electrode being electrically connected to the first chip mounting portion;a second semiconductor chip including a low side MOSFET of the DC-DC converter, the second semiconductor chip being mounted over the second chip mounting portion, the second semiconductor chip having an obverse surface, a reverse surface opposite the obverse surface, a first side, and a second side intersecting the first side,the second semiconductor chip having a second gate electrode pad and a second source electrode pad on the obverse surface, and a second drain electrode on the reverse surface,the second drain electrode being electrically connected to the second chip mounting portion;a third semiconductor chip including a first driver circuit to drive the high side MOSFET and a second driver circuit to drive the low side MOSFET, the third semiconductor chip being mounted over the third chip mounting portion, the third semiconductor chip having an obverse surface, a reverse surface, a first side, and a second side intersecting the first side,the third semiconductor chip having a first electrode pad electrically connected to the first driver circuit and a second electrode pad electrically connected to the second driver circuit;a sealing body sealing the first, second, and third semiconductor chips,portions of the first, second, third, and fourth leads and portions of the first, second, and third chip mounting portions being exposed from the sealing body;a first conductive material connected to the first source electrode pad of the first semiconductor chip and the second chip mounting portion; anda second conductive material connected to the second source electrode pad of the second semiconductor chip and the fourth lead,wherein the first semiconductor chip is disposed over the first chip mounting portion such that the first side of the first semiconductor chip faces the first side of the third semiconductor chip,wherein the second semiconductor chip is disposed over the second chip mounting portion such that the second side of the second semiconductor chip faces the second sides of the first and third semiconductor chips,wherein the gate electrode pad of the first semiconductor chip is connected to the first electrode pad of the third semiconductor chip via a first metal wire,wherein the gate electrode pad of the second semiconductor chip is connected to the second electrode pad of the third semiconductor chip via a second metal wire, andwherein the first metal wire overlaps the first sides of the first and third semiconductor chips in plan view, and the second metal wire overlaps the second sides of the second and third semiconductor chips in plan view. 2. A semiconductor device according to claim 1, wherein the first, second, and third semiconductor chips have quadrangle shapes in plan view,wherein the first semiconductor chip has a third side opposite the first side,wherein the second semiconductor chip has a third side opposite the second side,wherein the third semiconductor chip has third and fourth sides opposite the first and second sides, respectively,wherein the first gate electrode pad is disposed on the obverse surface of the first semiconductor chip such that the first gate electrode pad is closer to the first side of the first semiconductor chip than to the third side of the first semiconductor chip,wherein the second gate electrode pad is disposed on the obverse surface of the second semiconductor chip such that the second gate electrode pad is closer to the second side of the second semiconductor chip than to the third side of the second semiconductor chip,wherein the first electrode pad is disposed on the obverse surface of the third semiconductor chip such that the first electrode pad is closer to the first side of the second semiconductor chip than to the third side of the second semiconductor chip, andwherein the second electrode pad is disposed on the obverse surface of the third semiconductor chip such that the second electrode pad is closer to the second side of the second semiconductor chip than to the fourth side of the second semiconductor chip. 3. A semiconductor device according to claim 1, wherein the first side of the second semiconductor chip is closer to the third semiconductor chip than to the first semiconductor chip, andwherein the second gate electrode pad is disposed at a corner formed by the first and second sides of the second semiconductor chip. 4. A semiconductor device according to claim 1, wherein the first conductive material connects an exposed part of second chip mounting portion between the first and second semiconductor chips. 5. A semiconductor device according to claim 4, wherein the first conductive material overlaps the second side of the first semiconductor chip in plan view. 6. A semiconductor device according to claim 1, wherein a part of the first source electrode pad is disposed between the third side of the first semiconductor chip and the first gate electrode pad of the first semiconductor chip in plan view. 7. A semiconductor device according to claim 1, wherein at least one of the first conductive material and the second conductive material is a metal plate. 8. A semiconductor device according to claim 1, wherein at least one of the first conductive material and the second conductive material is a plurality of metal wires. 9. A semiconductor device according to claim 1, wherein the first metal wire is disposed so as to overlap in plan view the first side of the first semiconductor chip. 10. A semiconductor device according to claim 9, wherein the second side of the first semiconductor chip is longer than the first side of the first semiconductor chip. 11. A semiconductor device according to claim 1, wherein the second metal wire is disposed so as to overlap in plan view the second side of the second semiconductor chip. 12. A semiconductor device according to claim 11, wherein the first semiconductor chip has a third side intersecting the second side and a fourth side intersecting the first side, the second and fourth sides each being longer than the first side of the second semiconductor chip. 13. A semiconductor device according to claim 12, wherein the second semiconductor chip has a rectangular shape in plan view, second side is a long side of the rectangular shape, and the first side is a short side of the rectangular shape. 14. A semiconductor device according to claim 1, wherein the first gate electrode pad of the first semiconductor chip is exposed from the first conductive material, andwherein the second gate electrode pad of the second semiconductor chip is exposed from the second conductive material. 15. A semiconductor device according to claim 1, wherein respective widths of the first and second conductive materials are greater than respective diameters of the first and second metal wires. 16. A semiconductor device according to claim 1, wherein the first and second conductive materials are comprised of copper. 17. A semiconductor device according to claim 1, wherein the sealing body has a top surface and a bottom surface opposite the top surface, andwherein the exposed portions of the first, second, and third chip mounting portions are exposed from the bottom surface of the sealing body. 18. A semiconductor device according to claim 1, wherein the sealing body has a pair of first side surfaces and a pair of second side surfaces intersecting the first side surfaces, andwherein the fourth lead is disposed along one of the first side surfaces and one of the second side surfaces of the sealing body. 19. A semiconductor device according to claim 1, wherein the fourth lead is disposed around the second chip mounting portion and has a first portion thereof opposite the first side of the second semiconductor chip, and a second portion thereof opposite the second side of the second semiconductor chip, andwherein the second conductive material is coupled to the first and second portions of the fourth lead.
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